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| author | Daniel Jurgens <danielj@mellanox.com> | 2019-12-06 01:58:10 +0300 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2021-03-31 23:12:23 +0300 |
| commit | a7b76002ae78cd230ee652ccdfedf21aa94fcecc (patch) | |
| tree | 29ebc7b3b1990fcada3cb7bc450e28cb71e139a3 /drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c | |
| parent | 6f4fdd530a09c8e2c7368ba5a5b1711e6e5ced10 (diff) | |
| download | linux-a7b76002ae78cd230ee652ccdfedf21aa94fcecc.tar.xz | |
net/mlx5: Don't request more than supported EQs
Calculating the number of compeltion EQs based on the number of
available IRQ vectors doesn't work now that all async EQs share one IRQ.
Thus the max number of EQs can be exceeded on systems with more than
approximately 256 CPUs. Take this into account when calculating the
number of available completion EQs.
Fixes: 81bfa206032a ("net/mlx5: Use a single IRQ for all async EQs")
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c')
0 files changed, 0 insertions, 0 deletions