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authorRobert Marko <robimarko@gmail.com>2022-06-21 22:55:10 +0300
committerVinod Koul <vkoul@kernel.org>2022-07-05 10:25:52 +0300
commit2ec9bc8d1b0a742bce68b0f6b64a2500d882bf02 (patch)
tree47c55b32d9d8e363b95d6c2276af567d7fe3f3ec /drivers/phy
parentfe841d5ba7541b828bad98c2b9fa830e9078c575 (diff)
downloadlinux-2ec9bc8d1b0a742bce68b0f6b64a2500d882bf02.tar.xz
phy: qcom-qmp-pcie: make pipe clock rate configurable
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/qualcomm/phy-qcom-qmp-pcie.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 385ea3d8de08..d7ebd17ec0ef 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1284,6 +1284,9 @@ struct qmp_phy_cfg {
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* QMP PHY pipe clock interface rate */
+ unsigned long pipe_clock_rate;
};
/**
@@ -2121,8 +2124,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
init.ops = &clk_fixed_rate_ops;
- /* controllers using QMP phys use 125MHz pipe clock interface */
- fixed->fixed_rate = 125000000;
+ /*
+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
+ * unless other frequency is specified in the PHY config.
+ */
+ if (qmp->phys[0]->cfg->pipe_clock_rate)
+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
+ else
+ fixed->fixed_rate = 125000000;
+
fixed->hw.init = &init;
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);