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| author | Min Li <min.li.xe@renesas.com> | 2021-09-13 23:12:34 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-09-14 16:22:12 +0300 |
| commit | da9facf1c1825201956c2553e06d455dea3e0313 (patch) | |
| tree | 9a927a5003358ed85341da6159615df58d5d8ee0 /drivers/ptp/idt8a340_reg.h | |
| parent | 794c3dffacc166f7a8f7a555ff7e75fcdb644a51 (diff) | |
| download | linux-da9facf1c1825201956c2553e06d455dea3e0313.tar.xz | |
ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP
Also correct how initialize_dco_operating_mode is called
Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/idt8a340_reg.h')
| -rw-r--r-- | drivers/ptp/idt8a340_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/ptp/idt8a340_reg.h b/drivers/ptp/idt8a340_reg.h index dea8e1d6edaa..1c5210187110 100644 --- a/drivers/ptp/idt8a340_reg.h +++ b/drivers/ptp/idt8a340_reg.h @@ -635,6 +635,10 @@ #define STATE_MODE_SHIFT (0) #define STATE_MODE_MASK (0x7) +/* Bit definitions for the DPLL_MANU_REF_CFG register */ +#define MANUAL_REFERENCE_SHIFT (0) +#define MANUAL_REFERENCE_MASK (0x1f) + /* Bit definitions for the GPIO_CFG_GBL register */ #define SUPPLY_MODE_SHIFT (0) #define SUPPLY_MODE_MASK (0x3) |