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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-08-19 15:59:00 +0300
committerMark Brown <broonie@kernel.org>2020-08-21 00:38:13 +0300
commitfeace90233a8cd44a18902216657279c3932d471 (patch)
treedd76fa433e164725fc2f940b1fa265b9f76e768e /drivers/spi/spi-rspi.c
parent8dd71698607f822c3675c366a8a79bc82f7621f8 (diff)
downloadlinux-feace90233a8cd44a18902216657279c3932d471.tar.xz
spi: rspi: Increase bit rate accuracy on RZ/A
rspi_rz_set_config_register() favors high values of "brdv" over high values of "spbr". As "brdv" is not a plain divider, but controls a power-of-two divider, this may cause the selection of non-optimal divider values. E.g. on RSK+RZA1, when 3.8 MHz is requested, the actual configured bit rate is 2.08 MHz (spbr = 1, brdv = 3), while 3.7 MHz would be possible (spbr = 8, brdv = 0). Fix this by only resorting to higher "brdv" values when really needed. This makes the driver always pick optimal divider values on RZ/A. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200819125904.20938-4-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-rspi.c')
-rw-r--r--drivers/spi/spi-rspi.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 450a42ec2141..ad4ac867170b 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -298,15 +298,13 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
clksrc = clk_get_rate(rspi->clk);
- while (brdv < 3) {
- if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
- break;
+ spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
+ while (spbr > 255 && brdv < 3) {
brdv++;
- clksrc /= 2;
+ spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
}
/* Sets transfer bit rate */
- spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
rspi->spcmd |= SPCMD_BRDV(brdv);