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authorLinus Torvalds <torvalds@linux-foundation.org>2022-03-25 05:48:57 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2022-03-25 05:48:57 +0300
commit34af78c4e616c359ed428d79fe4758a35d2c5473 (patch)
treed7c27bfe3c9aa5b063bd630e27a70ff4a0db9069 /include/uapi
parent6f2689a7662809ff39f2b24e452d11569c21ea2f (diff)
parente17c6debd4b2d2d474074f83946f8c6522587566 (diff)
downloadlinux-34af78c4e616c359ed428d79fe4758a35d2c5473.tar.xz
Merge tag 'iommu-updates-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: - IOMMU Core changes: - Removal of aux domain related code as it is basically dead and will be replaced by iommu-fd framework - Split of iommu_ops to carry domain-specific call-backs separatly - Cleanup to remove useless ops->capable implementations - Improve 32-bit free space estimate in iova allocator - Intel VT-d updates: - Various cleanups of the driver - Support for ATS of SoC-integrated devices listed in ACPI/SATC table - ARM SMMU updates: - Fix SMMUv3 soft lockup during continuous stream of events - Fix error path for Qualcomm SMMU probe() - Rework SMMU IRQ setup to prepare the ground for PMU support - Minor cleanups and refactoring - AMD IOMMU driver: - Some minor cleanups and error-handling fixes - Rockchip IOMMU driver: - Use standard driver registration - MSM IOMMU driver: - Minor cleanup and change to standard driver registration - Mediatek IOMMU driver: - Fixes for IOTLB flushing logic * tag 'iommu-updates-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (47 commits) iommu/amd: Improve amd_iommu_v2_exit() iommu/amd: Remove unused struct fault.devid iommu/amd: Clean up function declarations iommu/amd: Call memunmap in error path iommu/arm-smmu: Account for PMU interrupts iommu/vt-d: Enable ATS for the devices in SATC table iommu/vt-d: Remove unused function intel_svm_capable() iommu/vt-d: Add missing "__init" for rmrr_sanity_check() iommu/vt-d: Move intel_iommu_ops to header file iommu/vt-d: Fix indentation of goto labels iommu/vt-d: Remove unnecessary prototypes iommu/vt-d: Remove unnecessary includes iommu/vt-d: Remove DEFER_DEVICE_DOMAIN_INFO iommu/vt-d: Remove domain and devinfo mempool iommu/vt-d: Remove iova_cache_get/put() iommu/vt-d: Remove finding domain in dmar_insert_one_dev_info() iommu/vt-d: Remove intel_iommu::domains iommu/mediatek: Always tlb_flush_all when each PM resume iommu/mediatek: Add tlb_lock in tlb_flush_all iommu/mediatek: Remove the power status checking in tlb flush all ...
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/linux/iommu.h181
1 files changed, 0 insertions, 181 deletions
diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h
index 59178fc229ca..65d8b0234f69 100644
--- a/include/uapi/linux/iommu.h
+++ b/include/uapi/linux/iommu.h
@@ -158,185 +158,4 @@ struct iommu_page_response {
__u32 code;
};
-/* defines the granularity of the invalidation */
-enum iommu_inv_granularity {
- IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */
- IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */
- IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */
- IOMMU_INV_GRANU_NR, /* number of invalidation granularities */
-};
-
-/**
- * struct iommu_inv_addr_info - Address Selective Invalidation Structure
- *
- * @flags: indicates the granularity of the address-selective invalidation
- * - If the PASID bit is set, the @pasid field is populated and the invalidation
- * relates to cache entries tagged with this PASID and matching the address
- * range.
- * - If ARCHID bit is set, @archid is populated and the invalidation relates
- * to cache entries tagged with this architecture specific ID and matching
- * the address range.
- * - Both PASID and ARCHID can be set as they may tag different caches.
- * - If neither PASID or ARCHID is set, global addr invalidation applies.
- * - The LEAF flag indicates whether only the leaf PTE caching needs to be
- * invalidated and other paging structure caches can be preserved.
- * @pasid: process address space ID
- * @archid: architecture-specific ID
- * @addr: first stage/level input address
- * @granule_size: page/block size of the mapping in bytes
- * @nb_granules: number of contiguous granules to be invalidated
- */
-struct iommu_inv_addr_info {
-#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0)
-#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1)
-#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2)
- __u32 flags;
- __u32 archid;
- __u64 pasid;
- __u64 addr;
- __u64 granule_size;
- __u64 nb_granules;
-};
-
-/**
- * struct iommu_inv_pasid_info - PASID Selective Invalidation Structure
- *
- * @flags: indicates the granularity of the PASID-selective invalidation
- * - If the PASID bit is set, the @pasid field is populated and the invalidation
- * relates to cache entries tagged with this PASID and matching the address
- * range.
- * - If the ARCHID bit is set, the @archid is populated and the invalidation
- * relates to cache entries tagged with this architecture specific ID and
- * matching the address range.
- * - Both PASID and ARCHID can be set as they may tag different caches.
- * - At least one of PASID or ARCHID must be set.
- * @pasid: process address space ID
- * @archid: architecture-specific ID
- */
-struct iommu_inv_pasid_info {
-#define IOMMU_INV_PASID_FLAGS_PASID (1 << 0)
-#define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1)
- __u32 flags;
- __u32 archid;
- __u64 pasid;
-};
-
-/**
- * struct iommu_cache_invalidate_info - First level/stage invalidation
- * information
- * @argsz: User filled size of this data
- * @version: API version of this structure
- * @cache: bitfield that allows to select which caches to invalidate
- * @granularity: defines the lowest granularity used for the invalidation:
- * domain > PASID > addr
- * @padding: reserved for future use (should be zero)
- * @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID
- * @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR
- *
- * Not all the combinations of cache/granularity are valid:
- *
- * +--------------+---------------+---------------+---------------+
- * | type / | DEV_IOTLB | IOTLB | PASID |
- * | granularity | | | cache |
- * +==============+===============+===============+===============+
- * | DOMAIN | N/A | Y | Y |
- * +--------------+---------------+---------------+---------------+
- * | PASID | Y | Y | Y |
- * +--------------+---------------+---------------+---------------+
- * | ADDR | Y | Y | N/A |
- * +--------------+---------------+---------------+---------------+
- *
- * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than
- * @version and @cache.
- *
- * If multiple cache types are invalidated simultaneously, they all
- * must support the used granularity.
- */
-struct iommu_cache_invalidate_info {
- __u32 argsz;
-#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1
- __u32 version;
-/* IOMMU paging structure cache */
-#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */
-#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */
-#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */
-#define IOMMU_CACHE_INV_TYPE_NR (3)
- __u8 cache;
- __u8 granularity;
- __u8 padding[6];
- union {
- struct iommu_inv_pasid_info pasid_info;
- struct iommu_inv_addr_info addr_info;
- } granu;
-};
-
-/**
- * struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest
- * SVA binding.
- *
- * @flags: VT-d PASID table entry attributes
- * @pat: Page attribute table data to compute effective memory type
- * @emt: Extended memory type
- *
- * Only guest vIOMMU selectable and effective options are passed down to
- * the host IOMMU.
- */
-struct iommu_gpasid_bind_data_vtd {
-#define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */
-#define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */
-#define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */
-#define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */
-#define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */
-#define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */
-#define IOMMU_SVA_VTD_GPASID_WPE (1 << 6) /* Write protect enable */
-#define IOMMU_SVA_VTD_GPASID_LAST (1 << 7)
- __u64 flags;
- __u32 pat;
- __u32 emt;
-};
-
-#define IOMMU_SVA_VTD_GPASID_MTS_MASK (IOMMU_SVA_VTD_GPASID_CD | \
- IOMMU_SVA_VTD_GPASID_EMTE | \
- IOMMU_SVA_VTD_GPASID_PCD | \
- IOMMU_SVA_VTD_GPASID_PWT)
-
-/**
- * struct iommu_gpasid_bind_data - Information about device and guest PASID binding
- * @argsz: User filled size of this data
- * @version: Version of this data structure
- * @format: PASID table entry format
- * @flags: Additional information on guest bind request
- * @gpgd: Guest page directory base of the guest mm to bind
- * @hpasid: Process address space ID used for the guest mm in host IOMMU
- * @gpasid: Process address space ID used for the guest mm in guest IOMMU
- * @addr_width: Guest virtual address width
- * @padding: Reserved for future use (should be zero)
- * @vtd: Intel VT-d specific data
- *
- * Guest to host PASID mapping can be an identity or non-identity, where guest
- * has its own PASID space. For non-identify mapping, guest to host PASID lookup
- * is needed when VM programs guest PASID into an assigned device. VMM may
- * trap such PASID programming then request host IOMMU driver to convert guest
- * PASID to host PASID based on this bind data.
- */
-struct iommu_gpasid_bind_data {
- __u32 argsz;
-#define IOMMU_GPASID_BIND_VERSION_1 1
- __u32 version;
-#define IOMMU_PASID_FORMAT_INTEL_VTD 1
-#define IOMMU_PASID_FORMAT_LAST 2
- __u32 format;
- __u32 addr_width;
-#define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */
- __u64 flags;
- __u64 gpgd;
- __u64 hpasid;
- __u64 gpasid;
- __u8 padding[8];
- /* Vendor specific data */
- union {
- struct iommu_gpasid_bind_data_vtd vtd;
- } vendor;
-};
-
#endif /* _UAPI_IOMMU_H */