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authorJiri Kosina <jkosina@suse.cz>2023-11-01 02:07:35 +0300
committerJiri Kosina <jkosina@suse.cz>2023-11-01 02:07:35 +0300
commit20cd569d7ee8fce24e8753f0f43af6c420557b1f (patch)
treef559cfda594846795aa51c99d96f92d8c912851a /tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json
parent62cc9c3cb3ec1bf31cc116146185ed97b450836a (diff)
parenteeebfe6259ba2d5b0980eb7b0df384eb77e9e4f5 (diff)
downloadlinux-20cd569d7ee8fce24e8753f0f43af6c420557b1f.tar.xz
Merge branch 'for-6.7/config_pm' into for-linus
- #ifdef CONFIG_PM removal from HID code (Thomas Weißschuh)
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diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json
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+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json
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+[
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE",
+ "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores."
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL",
+ "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache."
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE",
+ "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD",
+ "PublicDescription": "TBD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_LMISS_RD",
+ "PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency."
+ }
+]