diff options
23 files changed, 280 insertions, 283 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index a1e1d1c206fa..9d61f5941289 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -22,8 +22,8 @@ #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) -#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) -#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) +#define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) +#define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) @@ -53,8 +53,8 @@ #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) -#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) -#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) +#define RING_MODE(base) _MMIO((base) + 0x29c) +#define GFX_DISABLE_LEGACY_MODE (1 << 3) #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h index 05531d43514f..0f9c5b0b8a3b 100644 --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h @@ -37,7 +37,7 @@ #define MI_FLUSH_DW_OP_STOREDW (1<<14) #define MI_FLUSH_DW_USE_GTT (1<<2) -#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) +#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 1) #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3) #define SRC_ACCESS_TYPE_SHIFT 21 diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index fb91f04c3c6c..5a0a08c84f3d 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -10,18 +10,18 @@ /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 -#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 -#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) - -#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4) -#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4) -#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84) +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 +#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 +#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 +#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) + +#define FORCEWAKE_ACK_MEDIA_VDBOX(n) _MMIO(0xd50 + (n) * 4) +#define FORCEWAKE_ACK_MEDIA_VEBOX(n) _MMIO(0xd70 + (n) * 4) +#define FORCEWAKE_ACK_RENDER _MMIO(0xd84) #define GMD_ID _MMIO(0xd8c) #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) @@ -30,49 +30,49 @@ #define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc) -#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ +#define LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ #define LNCFCMOCS_REG_COUNT 32 #define MCFG_MCR_SELECTOR _MMIO(0xfd0) #define MTL_MCR_SELECTOR _MMIO(0xfd4) #define SF_MCR_SELECTOR _MMIO(0xfd8) -#define GEN8_MCR_SELECTOR _MMIO(0xfdc) +#define MCR_SELECTOR _MMIO(0xfdc) #define GAM_MCR_SELECTOR _MMIO(0xfe0) -#define GEN11_MCR_MULTICAST REG_BIT(31) -#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) -#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) -#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) -#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) +#define MCR_MULTICAST REG_BIT(31) +#define MCR_SLICE(slice) (((slice) & 0xf) << 27) +#define MCR_SLICE_MASK MCR_SLICE(0xf) +#define MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) +#define MCR_SUBSLICE_MASK MCR_SUBSLICE(0x7) #define MTL_MCR_GROUPID REG_GENMASK(11, 8) #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) -#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) -#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) +#define FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) +#define FFSC_PERCTX_PREEMPT_CTRL (1 << 14) #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) #define PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) -#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) +#define CS_DEBUG_MODE1 _MMIO(0x20ec) #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) -#define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0) +#define REPLAY_MODE_GRANULARITY REG_BIT(0) #define PS_INVOCATION_COUNT _MMIO(0x2348) -#define GEN8_CS_CHICKEN1 _MMIO(0x2580) -#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) -#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) -#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) -#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) -#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) -#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) +#define CS_CHICKEN1 _MMIO(0x2580) +#define PREEMPT_3D_OBJECT_LEVEL (1 << 0) +#define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) +#define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0) +#define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1) +#define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0) +#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1) -#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ -#define GEN12_CCS_AUX_INV _MMIO(0x4208) +#define GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ +#define CCS_AUX_INV _MMIO(0x4208) -#define GEN12_VD0_AUX_INV _MMIO(0x4218) -#define GEN12_VE0_AUX_INV _MMIO(0x4238) +#define VD0_AUX_INV _MMIO(0x4218) +#define VE0_AUX_INV _MMIO(0x4238) -#define GEN12_VE1_AUX_INV _MMIO(0x42b8) +#define VE1_AUX_INV _MMIO(0x42b8) #define AUX_INV REG_BIT(0) #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) @@ -88,7 +88,7 @@ #define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) -#define GEN12_FF_MODE2 _MMIO(0x6604) +#define FF_MODE2 _MMIO(0x6604) #define XEHP_FF_MODE2 MCR_REG(0x6604) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) @@ -101,22 +101,21 @@ #define XEHP_PSS_MODE2 MCR_REG(0x703c) #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) -#define HIZ_CHICKEN _MMIO(0x7018) +#define HIZ_CHICKEN _MMIO(0x7018) #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) -#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) +#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) -/* GEN7 chicken */ -#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) +#define COMMON_SLICE_CHICKEN1 _MMIO(0x7010) #define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) -#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) -#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) +#define COMMON_SLICE_CHICKEN3 _MMIO(0x7304) +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) -#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) -#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) -#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) +#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) +#define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) +#define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) @@ -130,21 +129,21 @@ #define XEHP_SQCM MCR_REG(0x8724) #define EN_32B_ACCESS REG_BIT(30) -#define GEN10_MIRROR_FUSE3 _MMIO(0x9118) -#define GEN10_L3BANK_PAIR_COUNT 4 -#define GEN10_L3BANK_MASK 0x0F +#define MIRROR_FUSE3 _MMIO(0x9118) +#define L3BANK_PAIR_COUNT 4 +#define L3BANK_MASK 0x0F /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ -#define GEN12_MAX_MSLICES 4 -#define GEN12_MEML3_EN_MASK 0x0F +#define MAX_MSLICES 4 +#define MEML3_EN_MASK 0x0F /* Fuse readout registers for GT */ #define XEHP_FUSE4 _MMIO(0x9114) #define GT_L3_EXC_MASK REG_GENMASK(6, 4) -#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) -#define GEN11_GT_VDBOX_DISABLE_MASK 0xff -#define GEN11_GT_VEBOX_DISABLE_SHIFT 16 -#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) +#define GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) +#define GT_VDBOX_DISABLE_MASK 0xff +#define GT_VEBOX_DISABLE_SHIFT 16 +#define GT_VEBOX_DISABLE_MASK (0x0f << GT_VEBOX_DISABLE_SHIFT) #define XELP_EU_ENABLE _MMIO(0x9134) /* "_DISABLE" on Xe_LP */ #define XELP_EU_MASK REG_GENMASK(7, 0) @@ -152,14 +151,13 @@ #define XEHP_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) -#define GEN6_GDRST _MMIO(0x941c) -#define GEN11_GRDOM_GUC REG_BIT(3) -#define GEN6_GRDOM_FULL (1 << 0) -#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL +#define GDRST _MMIO(0x941c) +#define GRDOM_GUC REG_BIT(3) +#define GRDOM_FULL REG_BIT(0) -#define GEN7_MISCCPCTL _MMIO(0x9424) -#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) -#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) +#define MISCCPCTL _MMIO(0x9424) +#define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) +#define DOP_CLOCK_GATE_ENABLE REG_BIT((0) #define UNSLCGCTL9430 _MMIO(0x9430) #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) @@ -213,10 +211,9 @@ #define L3_CR2X_CLKGATE_DIS REG_BIT(17) #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) -#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) -#define PSDUNIT_CLKGATE_DIS REG_BIT(5) +#define VSUNIT_CLKGATE2_DIS REG_BIT(19) -#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524) +#define SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524) #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) #define GWUNIT_CLKGATE_DIS REG_BIT(16) @@ -226,21 +223,21 @@ #define SSMCGCTL9530 MCR_REG(0x9530) #define RTFUNIT_CLKGATE_DIS REG_BIT(18) -#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550) +#define DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550) #define DFR_DISABLE (1 << 9) -#define GEN6_RPNSWREQ _MMIO(0xa008) +#define RPNSWREQ _MMIO(0xa008) #define REQ_RATIO_MASK REG_GENMASK(31, 23) -#define GEN6_RC_CONTROL _MMIO(0xa090) -#define GEN6_RC_STATE _MMIO(0xa094) +#define RC_CONTROL _MMIO(0xa090) +#define RC_STATE _MMIO(0xa094) -#define GEN6_PMINTRMSK _MMIO(0xa168) -#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) +#define PMINTRMSK _MMIO(0xa168) +#define PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) #define ARAT_EXPIRED_INTRMSK (1 << 9) -#define FORCEWAKE_GT_GEN9 _MMIO(0xa188) +#define FORCEWAKE_GT _MMIO(0xa188) -#define GEN9_PG_ENABLE _MMIO(0xa210) +#define PG_ENABLE _MMIO(0xa210) /* GPM unit config (Gen9+) */ #define CTC_MODE _MMIO(0xa26c) @@ -250,9 +247,9 @@ #define CTC_SHIFT_PARAMETER_SHIFT 1 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) -#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) -#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) -#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) +#define FORCEWAKE_RENDER _MMIO(0xa278) +#define FORCEWAKE_MEDIA_VDBOX(n) _MMIO(0xa540 + (n) * 4) +#define FORCEWAKE_MEDIA_VEBOX(n) _MMIO(0xa560 + (n) * 4) #define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) #define XEHPC_OVRLSCCC REG_BIT(0) @@ -282,12 +279,12 @@ #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) #define GLOBAL_INVALIDATION_MODE REG_BIT(2) -#define GEN10_SAMPLER_MODE MCR_REG(0xe18c) +#define SAMPLER_MODE MCR_REG(0xe18c) #define ENABLE_SMALLPL REG_BIT(15) #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) -#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) +#define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) -#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) +#define HALF_SLICE_CHICKEN7 MCR_REG(0xe194) #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) #define CACHE_MODE_SS MCR_REG(0xe420) @@ -295,27 +292,27 @@ #define DISABLE_ECC REG_BIT(5) #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) -#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c) -#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13) +#define ROW_CHICKEN4 MCR_REG(0xe48c) +#define DISABLE_GRF_CLEAR REG_BIT(13) #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) -#define GEN12_DISABLE_TDL_PUSH REG_BIT(9) -#define GEN11_DIS_PICK_2ND_EU REG_BIT(7) -#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) +#define DISABLE_TDL_PUSH REG_BIT(9) +#define DIS_PICK_2ND_EU REG_BIT(7) +#define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) -#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) +#define ROW_CHICKEN MCR_REG(0xe4f0) #define UGM_BACKUP_MODE REG_BIT(13) #define MDQ_ARBITRATION_MODE REG_BIT(12) -#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4) -#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15) -#define GEN12_DISABLE_EARLY_READ REG_BIT(14) -#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12) -#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) -#define GEN12_DISABLE_DOP_GATING REG_BIT(0) +#define ROW_CHICKEN2 MCR_REG(0xe4f4) +#define DISABLE_READ_SUPPRESSION REG_BIT(15) +#define DISABLE_EARLY_READ REG_BIT(14) +#define ENABLE_LARGE_GRF_MODE REG_BIT(12) +#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) +#define DISABLE_DOP_GATING REG_BIT(0) -#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) +#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define RT_CTRL MCR_REG(0xe530) @@ -335,21 +332,21 @@ #define SARB_CHICKEN1 MCR_REG(0xe90c) #define COMP_CKN_IN REG_GENMASK(30, 29) -#define GEN12_RCU_MODE _MMIO(0x14800) -#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define RCU_MODE _MMIO(0x14800) +#define RCU_MODE_CCS_ENABLE REG_BIT(0) -#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) +#define FORCEWAKE_ACK_GT _MMIO(0x130044) #define FORCEWAKE_KERNEL BIT(0) #define FORCEWAKE_USER BIT(1) #define FORCEWAKE_KERNEL_FALLBACK BIT(15) -#define GEN6_GT_CORE_STATUS _MMIO(0x138060) +#define GT_CORE_STATUS _MMIO(0x138060) #define RCN_MASK REG_GENMASK(2, 0) #define GT_RC0 0 #define GT_RC6 3 -#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) -#define GEN6_GT_GFX_RC6 _MMIO(0x138108) +#define GT_GFX_RC6_LOCKED _MMIO(0x138104) +#define GT_GFX_RC6 _MMIO(0x138108) #define GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h index 1960f9e78ec4..bc9b42b38795 100644 --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h @@ -54,23 +54,21 @@ #define HUC_STATUS2 _MMIO(0xd3b0) #define HUC_FW_VERIFIED REG_BIT(7) -#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc) +#define HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc) #define HUC_LOAD_SUCCESSFUL REG_BIT(0) #define GUC_WOPCM_SIZE _MMIO(0xc050) #define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12) #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0) -#define GEN8_GT_PM_CONFIG _MMIO(0x138140) -#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) -#define GEN9_GT_PM_CONFIG _MMIO(0x13816c) +#define GT_PM_CONFIG _MMIO(0x13816c) #define GT_DOORBELL_ENABLE REG_BIT(0) -#define GEN8_GTCR _MMIO(0x4274) -#define GEN8_GTCR_INVALIDATE REG_BIT(0) +#define GTCR _MMIO(0x4274) +#define GTCR_INVALIDATE REG_BIT(0) -#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8) -#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) +#define GUC_TLB_INV_CR _MMIO(0xcee8) +#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define GUC_ARAT_C6DIS _MMIO(0xa178) @@ -79,11 +77,11 @@ #define PVC_GUC_MOCS_UC_INDEX 1 #define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \ index) -#define GUC_GEN10_SHIM_WC_ENABLE REG_BIT(21) +#define GUC_SHIM_WC_ENABLE REG_BIT(21) #define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15) #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10) #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9) -#define GUC_GEN10_MSGCH_ENABLE REG_BIT(4) +#define GUC_MSGCH_ENABLE REG_BIT(4) #define GUC_ENABLE_MIA_CACHING REG_BIT(2) #define GUC_ENABLE_READ_CACHE_LOGIC REG_BIT(1) #define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0) @@ -91,7 +89,7 @@ #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_TRIGGER REG_BIT(0) -#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) +#define GUC_HOST_INTERRUPT _MMIO(0x1901f0) #define GUC_NUM_DOORBELLS 256 @@ -105,13 +103,13 @@ struct guc_doorbell_info { u32 reserved[14]; } __packed; -#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) -#define GEN8_DRB_VALID REG_BIT(0) -#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) +#define DRBREGL(x) _MMIO(0x1000 + (x) * 8) +#define DRB_VALID REG_BIT(0) +#define DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) -#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08) -#define GEN12_DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16) -#define GEN12_SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0) +#define DIST_DBS_POPULATED _MMIO(0xd08) +#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16) +#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0) #define GUC_BCS_RCS_IER _MMIO(0xC550) #define GUC_VCS2_VCS1_IER _MMIO(0xC554) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index c2a278b25fc9..50fc3c469086 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -11,23 +11,22 @@ #define LMEM_INIT REG_BIT(7) #define RENDER_RING_BASE 0x02000 -#define GEN11_BSD_RING_BASE 0x1c0000 -#define GEN11_BSD2_RING_BASE 0x1c4000 -#define GEN11_BSD3_RING_BASE 0x1d0000 -#define GEN11_BSD4_RING_BASE 0x1d4000 +#define BSD_RING_BASE 0x1c0000 +#define BSD2_RING_BASE 0x1c4000 +#define BSD3_RING_BASE 0x1d0000 +#define BSD4_RING_BASE 0x1d4000 #define XEHP_BSD5_RING_BASE 0x1e0000 #define XEHP_BSD6_RING_BASE 0x1e4000 #define XEHP_BSD7_RING_BASE 0x1f0000 #define XEHP_BSD8_RING_BASE 0x1f4000 -#define VEBOX_RING_BASE 0x1a000 -#define GEN11_VEBOX_RING_BASE 0x1c8000 -#define GEN11_VEBOX2_RING_BASE 0x1d8000 +#define VEBOX_RING_BASE 0x1c8000 +#define VEBOX2_RING_BASE 0x1d8000 #define XEHP_VEBOX3_RING_BASE 0x1e8000 #define XEHP_VEBOX4_RING_BASE 0x1f8000 -#define GEN12_COMPUTE0_RING_BASE 0x1a000 -#define GEN12_COMPUTE1_RING_BASE 0x1c000 -#define GEN12_COMPUTE2_RING_BASE 0x1e000 -#define GEN12_COMPUTE3_RING_BASE 0x26000 +#define COMPUTE0_RING_BASE 0x1a000 +#define COMPUTE1_RING_BASE 0x1c000 +#define COMPUTE2_RING_BASE 0x1e000 +#define COMPUTE3_RING_BASE 0x26000 #define BLT_RING_BASE 0x22000 #define XEHPC_BCS1_RING_BASE 0x3e0000 #define XEHPC_BCS2_RING_BASE 0x3e2000 @@ -43,8 +42,8 @@ #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) #define GT_RENDER_USER_INTERRUPT (1 << 0) -#define GEN7_FF_THREAD_MODE _MMIO(0x20a0) -#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) +#define FF_THREAD_MODE _MMIO(0x20a0) +#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) #define PVC_RP_STATE_CAP _MMIO(0x281014) #define MTL_RP_STATE_CAP _MMIO(0x138000) @@ -86,18 +85,18 @@ #define DG1_MSTR_IRQ REG_BIT(31) #define DG1_MSTR_TILE(t) REG_BIT(t) -#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) +#define TIMESTAMP_OVERRIDE _MMIO(0x44074) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) #define GGC _MMIO(0x108040) #define GMS_MASK REG_GENMASK(15, 8) #define GGMS_MASK REG_GENMASK(7, 6) -#define GEN12_GSMBASE _MMIO(0x108100) -#define GEN12_DSMBASE _MMIO(0x1080C0) -#define GEN12_BDSM_MASK REG_GENMASK64(63, 20) +#define GSMBASE _MMIO(0x108100) +#define DSMBASE _MMIO(0x1080C0) +#define BDSM_MASK REG_GENMASK64(63, 20) #endif diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c index 64b520ddca9c..d524ac5c7b57 100644 --- a/drivers/gpu/drm/xe/xe_execlist.c +++ b/drivers/gpu/drm/xe/xe_execlist.c @@ -60,8 +60,8 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, } if (hwe->class == XE_ENGINE_CLASS_COMPUTE) - xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg, - _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); + xe_mmio_write32(hwe->gt, RCU_MODE.reg, + _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); lrc->ring.old_tail = lrc->ring.tail; @@ -81,8 +81,8 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg, xe_bo_ggtt_addr(hwe->hwsp)); xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg); - xe_mmio_write32(gt, RING_MODE_GEN7(hwe->mmio_base).reg, - _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); + xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg, + _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE)); xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base).reg, lower_32_bits(lrc_desc)); diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c index 77a210acfac3..53d73f36a121 100644 --- a/drivers/gpu/drm/xe/xe_force_wake.c +++ b/drivers/gpu/drm/xe/xe_force_wake.c @@ -49,14 +49,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw) if (xe->info.graphics_verx100 >= 1270) { domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT], XE_FW_DOMAIN_ID_GT, - FORCEWAKE_GT_GEN9.reg, + FORCEWAKE_GT.reg, FORCEWAKE_ACK_GT_MTL.reg, BIT(0), BIT(16)); } else { domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT], XE_FW_DOMAIN_ID_GT, - FORCEWAKE_GT_GEN9.reg, - FORCEWAKE_ACK_GT_GEN9.reg, + FORCEWAKE_GT.reg, + FORCEWAKE_ACK_GT.reg, BIT(0), BIT(16)); } } @@ -71,8 +71,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) if (!xe_gt_is_media_type(gt)) domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER], XE_FW_DOMAIN_ID_RENDER, - FORCEWAKE_RENDER_GEN9.reg, - FORCEWAKE_ACK_RENDER_GEN9.reg, + FORCEWAKE_RENDER.reg, + FORCEWAKE_ACK_RENDER.reg, BIT(0), BIT(16)); for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) { @@ -81,8 +81,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j], XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j, - FORCEWAKE_MEDIA_VDBOX_GEN11(j).reg, - FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(j).reg, + FORCEWAKE_MEDIA_VDBOX(j).reg, + FORCEWAKE_ACK_MEDIA_VDBOX(j).reg, BIT(0), BIT(16)); } @@ -92,8 +92,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j], XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j, - FORCEWAKE_MEDIA_VEBOX_GEN11(j).reg, - FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(j).reg, + FORCEWAKE_MEDIA_VEBOX(j).reg, + FORCEWAKE_ACK_MEDIA_VEBOX(j).reg, BIT(0), BIT(16)); } } diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index 10a262a0c4cd..fc580d961dbb 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -185,12 +185,12 @@ err: return err; } -#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8) -#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) +#define GUC_TLB_INV_CR _MMIO(0xcee8) +#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c) -#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) +#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) #define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80) -#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) +#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) void xe_ggtt_invalidate(struct xe_gt *gt) { @@ -212,8 +212,8 @@ void xe_ggtt_invalidate(struct xe_gt *gt) xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg, PVC_GUC_TLB_INV_DESC0_VALID); } else - xe_mmio_write32(gt, GEN12_GUC_TLB_INV_CR.reg, - GEN12_GUC_TLB_INV_CR_INVALIDATE); + xe_mmio_write32(gt, GUC_TLB_INV_CR.reg, + GUC_TLB_INV_CR_INVALIDATE); } } diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 4186f7f0d42f..0d4664e344da 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -541,8 +541,8 @@ static int do_gt_reset(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); int err; - xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL); - err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000, + xe_mmio_write32(gt, GDRST.reg, GRDOM_FULL); + err = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_FULL, 5000, NULL, false); if (err) drm_err(&xe->drm, diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c index 60a2966bc1fd..1b7d00284535 100644 --- a/drivers/gpu/drm/xe/xe_gt_clock.c +++ b/drivers/gpu/drm/xe/xe_gt_clock.c @@ -14,16 +14,16 @@ static u32 read_reference_ts_freq(struct xe_gt *gt) { - u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg); + u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg); u32 base_freq, frac_freq; - base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; + base_freq = ((ts_override & TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> + TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; base_freq *= 1000000; frac_freq = ((ts_override & - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> - GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); + TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> + TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); frac_freq = 1000000 / (frac_freq + 1); return base_freq + frac_freq; @@ -36,17 +36,17 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg) const u32 f25_mhz = 25000000; const u32 f38_4_mhz = 38400000; u32 crystal_clock = - (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; + (rpm_config_reg & RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> + RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; switch (crystal_clock) { - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ : return f24_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ : return f19_2_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ : return f38_4_mhz; - case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: + case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ : return f25_mhz; default: XE_BUG_ON("NOT_POSSIBLE"); @@ -74,8 +74,8 @@ int xe_gt_clock_init(struct xe_gt *gt) * register increments from this frequency (it might * increment only every few clock cycle). */ - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + freq >>= 3 - ((c0 & RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> + RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); } gt->info.clock_freq = freq; diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c index 5412f77bc26f..aa04ba5a6dbe 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.c +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c @@ -177,8 +177,8 @@ static const struct xe_mmio_range dg2_implicit_steering_table[] = { static void init_steering_l3bank(struct xe_gt *gt) { if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { - u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK, xe_mmio_read32(gt, XEHP_FUSE4.reg)); @@ -190,8 +190,8 @@ static void init_steering_l3bank(struct xe_gt *gt) gt->steering[L3BANK].instance_target = bank_mask & BIT(0) ? 0 : 2; } else if (gt_to_xe(gt)->info.platform == XE_DG2) { - u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); u32 bank = __ffs(mslice_mask) * 8; /* @@ -202,8 +202,8 @@ static void init_steering_l3bank(struct xe_gt *gt) gt->steering[L3BANK].group_target = (bank >> 2) & 0x7; gt->steering[L3BANK].instance_target = bank & 0x3; } else { - u32 fuse = REG_FIELD_GET(GEN10_L3BANK_MASK, - ~xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 fuse = REG_FIELD_GET(L3BANK_MASK, + ~xe_mmio_read32(gt, MIRROR_FUSE3.reg)); gt->steering[L3BANK].group_target = 0; /* unused */ gt->steering[L3BANK].instance_target = __ffs(fuse); @@ -212,8 +212,8 @@ static void init_steering_l3bank(struct xe_gt *gt) static void init_steering_mslice(struct xe_gt *gt) { - u32 mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, - xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg)); + u32 mask = REG_FIELD_GET(MEML3_EN_MASK, + xe_mmio_read32(gt, MIRROR_FUSE3.reg)); /* * mslice registers are valid (not terminated) if either the meml3 @@ -329,8 +329,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); if (xe->info.platform == XE_DG2) { - u32 steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, 0) | - REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, 2); + u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) | + REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2); xe_mmio_write32(gt, MCFG_MCR_SELECTOR.reg, steer_val); xe_mmio_write32(gt, SF_MCR_SELECTOR.reg, steer_val); @@ -448,9 +448,9 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) | REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance); } else { - steer_reg = GEN8_MCR_SELECTOR.reg; - steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, group) | - REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, instance); + steer_reg = MCR_SELECTOR.reg; + steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) | + REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance); } /* @@ -461,7 +461,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag * No need to save old steering reg value. */ if (rw_flag == MCR_OP_READ) - steer_val |= GEN11_MCR_MULTICAST; + steer_val |= MCR_MULTICAST; xe_mmio_write32(gt, steer_reg, steer_val); @@ -477,7 +477,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag * operation. */ if (rw_flag == MCR_OP_WRITE) - xe_mmio_write32(gt, steer_reg, GEN11_MCR_MULTICAST); + xe_mmio_write32(gt, steer_reg, MCR_MULTICAST); return val; } diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index d18f2e25ce56..4e9e9b1aad02 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -278,7 +278,7 @@ int xe_guc_init(struct xe_guc *guc) if (xe_gt_is_media_type(gt)) guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT.reg; else - guc->notify_reg = GEN11_GUC_HOST_INTERRUPT.reg; + guc->notify_reg = GUC_HOST_INTERRUPT.reg; xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); @@ -317,9 +317,9 @@ int xe_guc_reset(struct xe_guc *guc) xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); - xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC); + xe_mmio_write32(gt, GDRST.reg, GRDOM_GUC); - ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000, + ret = xe_mmio_wait32(gt, GDRST.reg, 0, GRDOM_GUC, 5000, &gdrst, false); if (ret) { drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n", @@ -362,7 +362,7 @@ static void guc_prepare_xfer(struct xe_guc *guc) /* Must program this register before loading the ucode with DMA */ xe_mmio_write32(gt, GUC_SHIM_CONTROL.reg, shim_flags); - xe_mmio_write32(gt, GEN9_GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE); + xe_mmio_write32(gt, GT_PM_CONFIG.reg, GT_DOORBELL_ENABLE); } /* @@ -575,7 +575,7 @@ int xe_guc_enable_communication(struct xe_guc *guc) guc_enable_irq(guc); - xe_mmio_rmw32(guc_to_gt(guc), GEN6_PMINTRMSK.reg, + xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK.reg, ARAT_EXPIRED_INTRMSK, 0); err = xe_guc_ct_enable(&guc->ct); diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index d4fc2d357a78..6a723bda2aa9 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -450,10 +450,10 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, u32 flags; bool skip; } *e, extra_regs[] = { - { .reg = RING_MODE_GEN7(hwe->mmio_base).reg, }, + { .reg = RING_MODE(hwe->mmio_base).reg, }, { .reg = RING_HWS_PGA(hwe->mmio_base).reg, }, { .reg = RING_IMR(hwe->mmio_base).reg, }, - { .reg = GEN12_RCU_MODE.reg, .flags = 0x3, + { .reg = RCU_MODE.reg, .flags = 0x3, .skip = hwe != hwe_rcs_reset_domain }, }; u32 i; @@ -478,7 +478,8 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) { for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { guc_mmio_regset_write_one(ads, regset_map, - GEN9_LNCFCMOCS(i).reg, 0, count++); + LNCFCMOCS(i).reg, 0, + count++); } } @@ -557,11 +558,11 @@ static void guc_doorbell_init(struct xe_guc_ads *ads) if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) { u32 distdbreg = - xe_mmio_read32(gt, GEN12_DIST_DBS_POPULATED.reg); + xe_mmio_read32(gt, DIST_DBS_POPULATED.reg); ads_blob_write(ads, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], - REG_FIELD_GET(GEN12_DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1); + REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1); } } diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 0b6d0577a8a7..6d59e36b6e5c 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -413,7 +413,7 @@ static ssize_t freq_cur_show(struct device *dev, if (ret) goto out; - freq = xe_mmio_read32(gt, GEN6_RPNSWREQ.reg); + freq = xe_mmio_read32(gt, RPNSWREQ.reg); freq = REG_FIELD_GET(REQ_RATIO_MASK, freq); ret = sysfs_emit(buf, "%d\n", decode_freq(freq)); @@ -588,7 +588,7 @@ static ssize_t rc_status_show(struct device *dev, u32 reg; xe_device_mem_access_get(gt_to_xe(gt)); - reg = xe_mmio_read32(gt, GEN6_GT_CORE_STATUS.reg); + reg = xe_mmio_read32(gt, GT_CORE_STATUS.reg); xe_device_mem_access_put(gt_to_xe(gt)); switch (REG_FIELD_GET(RCN_MASK, reg)) { @@ -615,7 +615,7 @@ static ssize_t rc6_residency_show(struct device *dev, if (ret) goto out; - reg = xe_mmio_read32(gt, GEN6_GT_GFX_RC6.reg); + reg = xe_mmio_read32(gt, GT_GFX_RC6.reg); ret = sysfs_emit(buff, "%u\n", reg); XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); @@ -745,9 +745,9 @@ static int pc_gucrc_disable(struct xe_guc_pc *pc) if (ret) return ret; - xe_mmio_write32(gt, GEN9_PG_ENABLE.reg, 0); - xe_mmio_write32(gt, GEN6_RC_CONTROL.reg, 0); - xe_mmio_write32(gt, GEN6_RC_STATE.reg, 0); + xe_mmio_write32(gt, PG_ENABLE.reg, 0); + xe_mmio_write32(gt, RC_CONTROL.reg, 0); + xe_mmio_write32(gt, RC_STATE.reg, 0); XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); return 0; diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c index a1c3e54faa6e..55dcaab34ea4 100644 --- a/drivers/gpu/drm/xe/xe_huc.c +++ b/drivers/gpu/drm/xe/xe_huc.c @@ -84,7 +84,7 @@ int xe_huc_auth(struct xe_huc *huc) goto fail; } - ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg, + ret = xe_mmio_wait32(gt, HUC_KERNEL_LOAD_INFO.reg, HUC_LOAD_SUCCESSFUL, HUC_LOAD_SUCCESSFUL, 100000, NULL, false); if (ret) { @@ -126,7 +126,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p) return; drm_printf(p, "\nHuC status: 0x%08x\n", - xe_mmio_read32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg)); + xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO.reg)); xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); } diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 23b9f120c258..795302bcd3ae 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -110,28 +110,28 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_VIDEO_DECODE, .instance = 0, .domain = XE_FW_MEDIA_VDBOX0, - .mmio_base = GEN11_BSD_RING_BASE, + .mmio_base = BSD_RING_BASE, }, [XE_HW_ENGINE_VCS1] = { .name = "vcs1", .class = XE_ENGINE_CLASS_VIDEO_DECODE, .instance = 1, .domain = XE_FW_MEDIA_VDBOX1, - .mmio_base = GEN11_BSD2_RING_BASE, + .mmio_base = BSD2_RING_BASE, }, [XE_HW_ENGINE_VCS2] = { .name = "vcs2", .class = XE_ENGINE_CLASS_VIDEO_DECODE, .instance = 2, .domain = XE_FW_MEDIA_VDBOX2, - .mmio_base = GEN11_BSD3_RING_BASE, + .mmio_base = BSD3_RING_BASE, }, [XE_HW_ENGINE_VCS3] = { .name = "vcs3", .class = XE_ENGINE_CLASS_VIDEO_DECODE, .instance = 3, .domain = XE_FW_MEDIA_VDBOX3, - .mmio_base = GEN11_BSD4_RING_BASE, + .mmio_base = BSD4_RING_BASE, }, [XE_HW_ENGINE_VCS4] = { .name = "vcs4", @@ -166,14 +166,14 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, .instance = 0, .domain = XE_FW_MEDIA_VEBOX0, - .mmio_base = GEN11_VEBOX_RING_BASE, + .mmio_base = VEBOX_RING_BASE, }, [XE_HW_ENGINE_VECS1] = { .name = "vecs1", .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, .instance = 1, .domain = XE_FW_MEDIA_VEBOX1, - .mmio_base = GEN11_VEBOX2_RING_BASE, + .mmio_base = VEBOX2_RING_BASE, }, [XE_HW_ENGINE_VECS2] = { .name = "vecs2", @@ -194,28 +194,28 @@ static const struct engine_info engine_infos[] = { .class = XE_ENGINE_CLASS_COMPUTE, .instance = 0, .domain = XE_FW_RENDER, - .mmio_base = GEN12_COMPUTE0_RING_BASE, + .mmio_base = COMPUTE0_RING_BASE, }, [XE_HW_ENGINE_CCS1] = { .name = "ccs1", .class = XE_ENGINE_CLASS_COMPUTE, .instance = 1, .domain = XE_FW_RENDER, - .mmio_base = GEN12_COMPUTE1_RING_BASE, + .mmio_base = COMPUTE1_RING_BASE, }, [XE_HW_ENGINE_CCS2] = { .name = "ccs2", .class = XE_ENGINE_CLASS_COMPUTE, .instance = 2, .domain = XE_FW_RENDER, - .mmio_base = GEN12_COMPUTE2_RING_BASE, + .mmio_base = COMPUTE2_RING_BASE, }, [XE_HW_ENGINE_CCS3] = { .name = "ccs3", .class = XE_ENGINE_CLASS_COMPUTE, .instance = 3, .domain = XE_FW_RENDER, - .mmio_base = GEN12_COMPUTE3_RING_BASE, + .mmio_base = COMPUTE3_RING_BASE, }, }; @@ -254,14 +254,14 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) - xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg, - _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); + xe_mmio_write32(hwe->gt, RCU_MODE.reg, + _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); hw_engine_mmio_write32(hwe, RING_HWSTAM(0).reg, ~0x0); hw_engine_mmio_write32(hwe, RING_HWS_PGA(0).reg, xe_bo_ggtt_addr(hwe->hwsp)); - hw_engine_mmio_write32(hwe, RING_MODE_GEN7(0).reg, - _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); + hw_engine_mmio_write32(hwe, RING_MODE(0).reg, + _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE)); hw_engine_mmio_write32(hwe, RING_MI_MODE(0).reg, _MASKED_BIT_DISABLE(STOP_RING)); hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg); @@ -379,7 +379,7 @@ static void read_media_fuses(struct xe_gt *gt) xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); - media_fuse = xe_mmio_read32(gt, GEN11_GT_VEBOX_VDBOX_DISABLE.reg); + media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE.reg); /* * Pre-Xe_HP platforms had register bits representing absent engines, @@ -390,8 +390,8 @@ static void read_media_fuses(struct xe_gt *gt) if (GRAPHICS_VERx100(xe) < 1250) media_fuse = ~media_fuse; - vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse); - vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse); + vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse); + vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse); for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) { if (!(gt->info.engine_mask & BIT(i))) @@ -421,8 +421,8 @@ static void read_copy_fuses(struct xe_gt *gt) xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); - bcs_mask = xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg); - bcs_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, bcs_mask); + bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3.reg); + bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask); /* BCS0 is always present; only BCS1-BCS8 may be fused off */ for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) { @@ -546,7 +546,7 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p) drm_printf(p, "\tRING_MODE: 0x%08x\n", hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg)); drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n", - hw_engine_mmio_read32(hwe, RING_MODE_GEN7(0).reg)); + hw_engine_mmio_read32(hwe, RING_MODE(0).reg)); drm_printf(p, "\tRING_IMR: 0x%08x\n", hw_engine_mmio_read32(hwe, RING_IMR(0).reg)); @@ -573,8 +573,8 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p) hw_engine_mmio_read32(hwe, IPEHR(0).reg)); if (hwe->class == XE_ENGINE_CLASS_COMPUTE) - drm_printf(p, "\tGEN12_RCU_MODE: 0x%08x\n", - xe_mmio_read32(hwe->gt, GEN12_RCU_MODE.reg)); + drm_printf(p, "\tRCU_MODE: 0x%08x\n", + xe_mmio_read32(hwe->gt, RCU_MODE.reg)); } diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c index 5536f84682c0..9b466803c68e 100644 --- a/drivers/gpu/drm/xe/xe_mmio.c +++ b/drivers/gpu/drm/xe/xe_mmio.c @@ -158,7 +158,8 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_si if (!xe->info.has_flat_ccs) { *vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR); if (usable_size) - *usable_size = min(*vram_size, xe_mmio_read64(gt, GEN12_GSMBASE.reg)); + *usable_size = min(*vram_size, + xe_mmio_read64(gt, GSMBASE.reg)); return 0; } diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index e09c6242aafc..67c63facdbf9 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -512,8 +512,9 @@ static void init_l3cc_table(struct xe_gt *gt, (l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i), get_entry_l3cc(info, 2 * i + 1))), 1 : 0; i++) { - mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, GEN9_LNCFCMOCS(i).reg, l3cc); - xe_mmio_write32(gt, GEN9_LNCFCMOCS(i).reg, l3cc); + mocs_dbg(>->xe->drm, "%d 0x%x 0x%x\n", i, LNCFCMOCS(i).reg, + l3cc); + xe_mmio_write32(gt, LNCFCMOCS(i).reg, l3cc); } } @@ -531,7 +532,7 @@ void xe_mocs_init(struct xe_gt *gt) gt->mocs.wb_index = table.wb_index; if (flags & HAS_GLOBAL_MOCS) - __init_mocs_table(gt, &table, GEN12_GLOBAL_MOCS(0).reg); + __init_mocs_table(gt, &table, GLOBAL_MOCS(0).reg); /* * Initialize the L3CC table as part of mocs initalization to make diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c index c4b3a2045299..5a2665706912 100644 --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c @@ -31,7 +31,7 @@ static const struct xe_rtp_entry register_whitelist[] = { }, { XE_RTP_NAME("1508744258, 14012131227, 1808121037"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(WHITELIST(GEN7_COMMON_SLICE_CHICKEN1, 0)) + XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0)) }, { XE_RTP_NAME("1806527549"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index 5480746d40e8..4c5f46f89241 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -85,7 +85,7 @@ static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 *dw, int i) static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i) { - dw[i++] = MI_BATCH_BUFFER_START_GEN8 | ppgtt_flag; + dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag; dw[i++] = lower_32_bits(batch_addr); dw[i++] = upper_32_bits(batch_addr); @@ -202,9 +202,9 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, /* Wa_1809175790 */ if (!xe->info.has_flat_ccs) { if (decode) - i = emit_aux_table_inv(gt, GEN12_VD0_AUX_INV.reg, dw, i); + i = emit_aux_table_inv(gt, VD0_AUX_INV.reg, dw, i); else - i = emit_aux_table_inv(gt, GEN12_VE0_AUX_INV.reg, dw, i); + i = emit_aux_table_inv(gt, VE0_AUX_INV.reg, dw, i); } dw[i++] = preparser_disable(false); @@ -246,7 +246,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, i = emit_pipe_invalidate(mask_flags, dw, i); /* Wa_1809175790 */ if (!xe->info.has_flat_ccs) - i = emit_aux_table_inv(gt, GEN12_CCS_AUX_INV.reg, dw, i); + i = emit_aux_table_inv(gt, CCS_AUX_INV.reg, dw, i); dw[i++] = preparser_disable(false); i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c index 31887fec1073..9ce0a0585539 100644 --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c @@ -65,7 +65,7 @@ static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr) } /* Use DSM base address instead for stolen memory */ - mgr->stolen_base = xe_mmio_read64(gt, GEN12_DSMBASE.reg) & GEN12_BDSM_MASK; + mgr->stolen_base = xe_mmio_read64(gt, DSMBASE.reg) & BDSM_MASK; if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base)) return 0; diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index 27cf1330facd..43912312cfba 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -33,7 +33,7 @@ static const struct xe_rtp_entry lrc_tunings[] = { { XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), /* read verification is ignored due to 1608008084. */ - XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2, + XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224)) }, diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index a7d681b7538d..7a9bf588301e 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -105,7 +105,7 @@ static const struct xe_rtp_entry gt_was[] = { }, { XE_RTP_NAME("14011059788"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), - XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) + XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) }, /* DG1 */ @@ -116,7 +116,7 @@ static const struct xe_rtp_entry gt_was[] = { }, { XE_RTP_NAME("1408615072"), XE_RTP_RULES(PLATFORM(DG1)), - XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL)) + XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) }, /* DG2 */ @@ -134,7 +134,7 @@ static const struct xe_rtp_entry gt_was[] = { }, { XE_RTP_NAME("14011006942"), XE_RTP_RULES(SUBPLATFORM(DG2, G10)), - XE_RTP_ACTIONS(SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) + XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) }, { XE_RTP_NAME("14012362059"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)), @@ -197,7 +197,7 @@ static const struct xe_rtp_entry gt_was[] = { }, { XE_RTP_NAME("14015795083"), XE_RTP_RULES(PLATFORM(DG2)), - XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) + XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) }, { XE_RTP_NAME("18018781329"), XE_RTP_RULES(PLATFORM(DG2)), @@ -221,7 +221,7 @@ static const struct xe_rtp_entry gt_was[] = { { XE_RTP_NAME("14015795083"), XE_RTP_RULES(PLATFORM(PVC)), - XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)) + XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) }, { XE_RTP_NAME("18018781329"), XE_RTP_RULES(PLATFORM(PVC)), @@ -241,42 +241,42 @@ static const struct xe_rtp_entry gt_was[] = { static const struct xe_rtp_entry engine_was[] = { { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN7_FF_THREAD_MODE, - GEN12_FF_TESSELATION_DOP_GATE_DISABLE)) + XE_RTP_ACTIONS(SET(FF_THREAD_MODE, + FF_TESSELATION_DOP_GATE_DISABLE)) }, { XE_RTP_NAME("1409804808"), XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER), IS_INTEGRATED), - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS, + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14010229206, 1409085225"), XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER), IS_INTEGRATED), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("1606931601"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ, + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE, + XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("1406941453"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL, + XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1, - GEN9_FFSC_PERCTX_PREEMPT_CTRL, + XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1, + FFSC_PERCTX_PREEMPT_CTRL, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -285,8 +285,8 @@ static const struct xe_rtp_entry engine_was[] = { { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE, + WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -295,8 +295,8 @@ static const struct xe_rtp_entry engine_was[] = { { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE, + WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -305,8 +305,8 @@ static const struct xe_rtp_entry engine_was[] = { { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE, + WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -366,7 +366,7 @@ static const struct xe_rtp_entry engine_was[] = { { XE_RTP_NAME("14015227452"), XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("16015675438"), @@ -405,36 +405,36 @@ static const struct xe_rtp_entry engine_was[] = { }, { XE_RTP_NAME("1509727124"), XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB, + XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("22012856258"), XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION, + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14013392000"), XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE, + XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14012419201"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, - GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, + DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14012419201"), XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, - GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, + DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("1308578152"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(B0, C0), ENGINE_CLASS(RENDER), FUNC(xe_rtp_match_first_gslice_fused_off)), - XE_RTP_ACTIONS(CLR(GEN9_CS_DEBUG_MODE1, - GEN12_REPLAY_MODE_GRANULARITY, + XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1, + REPLAY_MODE_GRANULARITY, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("22010960976, 14013347512"), @@ -445,14 +445,14 @@ static const struct xe_rtp_entry engine_was[] = { }, { XE_RTP_NAME("1608949956, 14010198302"), XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN, + XE_RTP_ACTIONS(SET(ROW_CHICKEN, MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("22010430635"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, - GEN12_DISABLE_GRF_CLEAR, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, + DISABLE_GRF_CLEAR, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("14013202645"), @@ -465,13 +465,13 @@ static const struct xe_rtp_entry engine_was[] = { }, { XE_RTP_NAME("22012532006"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, C0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7, + XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("22012532006"), XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(GEN9_HALF_SLICE_CHICKEN7, + XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -507,7 +507,7 @@ static const struct xe_rtp_entry engine_was[] = { }, { XE_RTP_NAME("14015227452"), XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, + XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("16015675438"), @@ -526,15 +526,15 @@ static const struct xe_rtp_entry engine_was[] = { static const struct xe_rtp_entry lrc_was[] = { { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), - XE_RTP_ACTIONS(SET(GEN11_COMMON_SLICE_CHICKEN3, - GEN12_DISABLE_CPS_AWARE_COLOR_PIPE, + XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, + DISABLE_CPS_AWARE_COLOR_PIPE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), - XE_RTP_ACTIONS(FIELD_SET(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL, + XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1, + PREEMPT_GPGPU_LEVEL_MASK, + PREEMPT_GPGPU_THREAD_GROUP_LEVEL, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("1806527549"), @@ -552,7 +552,7 @@ static const struct xe_rtp_entry lrc_was[] = { { XE_RTP_NAME("1409044764"), XE_RTP_RULES(PLATFORM(DG1)), - XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3, + XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN, XE_RTP_ACTION_FLAG(MASKED_REG))) }, @@ -581,7 +581,7 @@ static const struct xe_rtp_entry lrc_was[] = { { XE_RTP_NAME("14010698770, 22010613112, 22010465075"), XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)), XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3, - GEN12_DISABLE_CPS_AWARE_COLOR_PIPE, + DISABLE_CPS_AWARE_COLOR_PIPE, XE_RTP_ACTION_FLAG(MASKED_REG))) }, { XE_RTP_NAME("16013271637"), |