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Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019.dtsi15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 02e9ea78405d..dfcfb3339c23 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -143,7 +143,6 @@
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
- clock-output-names = "gcc_sleep_clk_src";
#clock-cells = <0>;
};
@@ -190,6 +189,8 @@
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
};
prng: rng@22000 {
@@ -325,22 +326,22 @@
status = "disabled";
};
- acc0: clock-controller@b088000 {
+ acc0: power-manager@b088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
};
- acc1: clock-controller@b098000 {
+ acc1: power-manager@b098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
};
- acc2: clock-controller@b0a8000 {
+ acc2: power-manager@b0a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
};
- acc3: clock-controller@b0b8000 {
+ acc3: power-manager@b0b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
@@ -426,8 +427,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
- <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
+ ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
+ <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";