diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 343 |
1 files changed, 294 insertions, 49 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8141926e4ef1..f3531cfb0d79 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -789,6 +789,23 @@ reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; }; + pgc_mlmix: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, + <800000000>, + <300000000>; + }; + pgc_audio: power-domain@5 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; @@ -821,6 +838,12 @@ assigned-clock-rates = <800000000>, <400000000>; }; + pgc_vpumix: power-domain@8 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; + }; + pgc_gpu3d: power-domain@9 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_GPU3D>; @@ -836,69 +859,64 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; - pgc_mipi_phy2: power-domain@16 { + pgc_vpu_g1: power-domain@11 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; }; - pgc_hsiomix: power-domain@17 { + pgc_vpu_g2: power-domain@12 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, - <&clk IMX8MP_CLK_HSIO_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; - pgc_ispdwp: power-domain@18 { + pgc_vpu_vc8000e: power-domain@13 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; - pgc_vpumix: power-domain@19 { + pgc_hdmimix: power-domain@14 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; - clocks = <&clk IMX8MP_CLK_VPU_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; }; - pgc_vpu_g1: power-domain@20 { + pgc_hdmi_phy: power-domain@15 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; }; - pgc_vpu_g2: power-domain@21 { + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; }; - pgc_vpu_vc8000e: power-domain@22 { + pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; }; - pgc_mlmix: power-domain@24 { + pgc_ispdwp: power-domain@18 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MLMIX>; - clocks = <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>, - <&clk IMX8MP_CLK_NPU_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, - <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, - <800000000>, - <300000000>; + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; }; }; }; @@ -1513,6 +1531,41 @@ status = "disabled"; }; + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR PHY - SPDIF wakeup IRQ */ + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audio_blk_ctrl 0>; + status = "disabled"; + }; }; sdma3: dma-controller@30e00000 { @@ -1541,6 +1594,7 @@ compatible = "fsl,imx8mp-audio-blk-ctrl"; reg = <0x30e20000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_SAI1>, <&clk IMX8MP_CLK_SAI2>, @@ -1552,6 +1606,9 @@ "sai1", "sai2", "sai3", "sai5", "sai6", "sai7"; power-domains = <&pgc_audio>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; }; }; @@ -1616,6 +1673,50 @@ }; }; + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + dewarp: dwe@32e30000 { compatible = "nxp,imx8mp-dw100"; reg = <0x32e30000 0x10000>; @@ -1630,7 +1731,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <500000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1638,9 +1739,8 @@ clock-names = "pclk", "wrap", "phy", "axi"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <500000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1666,7 +1766,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e50000 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <266000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1674,9 +1774,8 @@ clock-names = "pclk", "wrap", "phy", "axi"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; status = "disabled"; @@ -1725,6 +1824,13 @@ remote-endpoint = <&lcdif1_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; @@ -1807,17 +1913,26 @@ clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", "isp", "phy"; + /* + * The ISP maximum frequency is 400MHz in normal mode + * and 500MHz in overdrive mode. The 400MHz operating + * point hasn't been successfully tested yet, so set + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. + */ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, <&clk IMX8MP_CLK_MEDIA_APB>, <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VIDEO_PLL1_OUT>, - <&clk IMX8MP_VIDEO_PLL1_OUT>; + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>, <200000000>, - <0>, <0>, <1039500000>; + <0>, <0>, <500000000>, + <1039500000>; #power-domain-cells = <1>; lvds_bridge: bridge@5c { @@ -1889,6 +2004,136 @@ #power-domain-cells = <1>; #clock-cells = <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells = <1>; + }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 { |