diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index 2205cb0204e7..06daf35bb587 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -76,18 +76,40 @@ type REFCLK_CLOCK_EN;\ type REFCLK_SRC_SEL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCCG3_REG_FIELD_LIST(type) \ + type PHYASYMCLK_FORCE_EN;\ + type PHYASYMCLK_FORCE_SRC_SEL;\ + type PHYBSYMCLK_FORCE_EN;\ + type PHYBSYMCLK_FORCE_SRC_SEL;\ + type PHYCSYMCLK_FORCE_EN;\ + type PHYCSYMCLK_FORCE_SRC_SEL; +#endif + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCCG3_REG_FIELD_LIST(uint8_t) +#endif }; struct dccg_mask { DCCG_REG_FIELD_LIST(uint32_t) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCCG3_REG_FIELD_LIST(uint32_t) +#endif }; struct dccg_registers { uint32_t DPPCLK_DTO_CTRL; uint32_t DPPCLK_DTO_PARAM[6]; uint32_t REFCLK_CNTL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint32_t HDMICHARCLK_CLOCK_CNTL[6]; + uint32_t PHYASYMCLK_CLOCK_CNTL; + uint32_t PHYBSYMCLK_CLOCK_CNTL; + uint32_t PHYCSYMCLK_CLOCK_CNTL; +#endif }; struct dcn_dccg { |