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path: root/drivers/mtd/nand/raw/fsl_upm.c
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Diffstat (limited to 'drivers/mtd/nand/raw/fsl_upm.c')
-rw-r--r--drivers/mtd/nand/raw/fsl_upm.c311
1 files changed, 112 insertions, 199 deletions
diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c
index 627deb26db51..197850aeb261 100644
--- a/drivers/mtd/nand/raw/fsl_upm.c
+++ b/drivers/mtd/nand/raw/fsl_upm.c
@@ -14,32 +14,23 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
-#include <linux/of_address.h>
#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/fsl_lbc.h>
-#define FSL_UPM_WAIT_RUN_PATTERN 0x1
-#define FSL_UPM_WAIT_WRITE_BYTE 0x2
-#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
-
struct fsl_upm_nand {
+ struct nand_controller base;
struct device *dev;
struct nand_chip chip;
- int last_ctrl;
- struct mtd_partition *parts;
struct fsl_upm upm;
uint8_t upm_addr_offset;
uint8_t upm_cmd_offset;
void __iomem *io_base;
- int rnb_gpio[NAND_MAX_CHIPS];
+ struct gpio_desc *rnb_gpio[NAND_MAX_CHIPS];
uint32_t mchip_offsets[NAND_MAX_CHIPS];
uint32_t mchip_count;
uint32_t mchip_number;
- int chip_delay;
- uint32_t wait_flags;
};
static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
@@ -48,106 +39,6 @@ static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
chip);
}
-static int fun_chip_ready(struct nand_chip *chip)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
-
- if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
- return 1;
-
- dev_vdbg(fun->dev, "busy\n");
- return 0;
-}
-
-static void fun_wait_rnb(struct fsl_upm_nand *fun)
-{
- if (fun->rnb_gpio[fun->mchip_number] >= 0) {
- struct mtd_info *mtd = nand_to_mtd(&fun->chip);
- int cnt = 1000000;
-
- while (--cnt && !fun_chip_ready(&fun->chip))
- cpu_relax();
- if (!cnt)
- dev_err(fun->dev, "tired waiting for RNB\n");
- } else {
- ndelay(100);
- }
-}
-
-static void fun_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
- u32 mar;
-
- if (!(ctrl & fun->last_ctrl)) {
- fsl_upm_end_pattern(&fun->upm);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
- }
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_ALE)
- fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
- else if (ctrl & NAND_CLE)
- fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
- }
-
- mar = (cmd << (32 - fun->upm.width)) |
- fun->mchip_offsets[fun->mchip_number];
- fsl_upm_run_pattern(&fun->upm, chip->legacy.IO_ADDR_R, mar);
-
- if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
- fun_wait_rnb(fun);
-}
-
-static void fun_select_chip(struct nand_chip *chip, int mchip_nr)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
-
- if (mchip_nr == -1) {
- chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
- } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
- fun->mchip_number = mchip_nr;
- chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
- chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
- } else {
- BUG();
- }
-}
-
-static uint8_t fun_read_byte(struct nand_chip *chip)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
-
- return in_8(fun->chip.legacy.IO_ADDR_R);
-}
-
-static void fun_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = in_8(fun->chip.legacy.IO_ADDR_R);
-}
-
-static void fun_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
-{
- struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
- int i;
-
- for (i = 0; i < len; i++) {
- out_8(fun->chip.legacy.IO_ADDR_W, buf[i]);
- if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
- fun_wait_rnb(fun);
- }
- if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
- fun_wait_rnb(fun);
-}
-
static int fun_chip_init(struct fsl_upm_nand *fun,
const struct device_node *upm_np,
const struct resource *io_res)
@@ -156,21 +47,9 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
int ret;
struct device_node *flash_np;
- fun->chip.legacy.IO_ADDR_R = fun->io_base;
- fun->chip.legacy.IO_ADDR_W = fun->io_base;
- fun->chip.legacy.cmd_ctrl = fun_cmd_ctrl;
- fun->chip.legacy.chip_delay = fun->chip_delay;
- fun->chip.legacy.read_byte = fun_read_byte;
- fun->chip.legacy.read_buf = fun_read_buf;
- fun->chip.legacy.write_buf = fun_write_buf;
fun->chip.ecc.mode = NAND_ECC_SOFT;
fun->chip.ecc.algo = NAND_ECC_HAMMING;
- if (fun->mchip_count > 1)
- fun->chip.legacy.select_chip = fun_select_chip;
-
- if (fun->rnb_gpio[0] >= 0)
- fun->chip.legacy.dev_ready = fun_chip_ready;
-
+ fun->chip.controller = &fun->base;
mtd->dev.parent = fun->dev;
flash_np = of_get_next_child(upm_np, NULL);
@@ -178,8 +57,9 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
return -ENODEV;
nand_set_flash_node(&fun->chip, flash_np);
- mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%pOFn", (u64)io_res->start,
- flash_np);
+ mtd->name = devm_kasprintf(fun->dev, GFP_KERNEL, "0x%llx.%pOFn",
+ (u64)io_res->start,
+ flash_np);
if (!mtd->name) {
ret = -ENOMEM;
goto err;
@@ -192,51 +72,130 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
ret = mtd_device_register(mtd, NULL, 0);
err:
of_node_put(flash_np);
- if (ret)
- kfree(mtd->name);
return ret;
}
+static int func_exec_instr(struct nand_chip *chip,
+ const struct nand_op_instr *instr)
+{
+ struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
+ u32 mar, reg_offs = fun->mchip_offsets[fun->mchip_number];
+ unsigned int i;
+ const u8 *out;
+ u8 *in;
+
+ switch (instr->type) {
+ case NAND_OP_CMD_INSTR:
+ fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
+ mar = (instr->ctx.cmd.opcode << (32 - fun->upm.width)) |
+ reg_offs;
+ fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
+ fsl_upm_end_pattern(&fun->upm);
+ return 0;
+
+ case NAND_OP_ADDR_INSTR:
+ fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
+ for (i = 0; i < instr->ctx.addr.naddrs; i++) {
+ mar = (instr->ctx.addr.addrs[i] << (32 - fun->upm.width)) |
+ reg_offs;
+ fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
+ }
+ fsl_upm_end_pattern(&fun->upm);
+ return 0;
+
+ case NAND_OP_DATA_IN_INSTR:
+ in = instr->ctx.data.buf.in;
+ for (i = 0; i < instr->ctx.data.len; i++)
+ in[i] = in_8(fun->io_base + reg_offs);
+ return 0;
+
+ case NAND_OP_DATA_OUT_INSTR:
+ out = instr->ctx.data.buf.out;
+ for (i = 0; i < instr->ctx.data.len; i++)
+ out_8(fun->io_base + reg_offs, out[i]);
+ return 0;
+
+ case NAND_OP_WAITRDY_INSTR:
+ if (!fun->rnb_gpio[fun->mchip_number])
+ return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
+
+ return nand_gpio_waitrdy(chip, fun->rnb_gpio[fun->mchip_number],
+ instr->ctx.waitrdy.timeout_ms);
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fun_exec_op(struct nand_chip *chip, const struct nand_operation *op,
+ bool check_only)
+{
+ struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
+ unsigned int i;
+ int ret;
+
+ if (op->cs > NAND_MAX_CHIPS)
+ return -EINVAL;
+
+ if (check_only)
+ return 0;
+
+ fun->mchip_number = op->cs;
+
+ for (i = 0; i < op->ninstrs; i++) {
+ ret = func_exec_instr(chip, &op->instrs[i]);
+ if (ret)
+ return ret;
+
+ if (op->instrs[i].delay_ns)
+ ndelay(op->instrs[i].delay_ns);
+ }
+
+ return 0;
+}
+
+static const struct nand_controller_ops fun_ops = {
+ .exec_op = fun_exec_op,
+};
+
static int fun_probe(struct platform_device *ofdev)
{
struct fsl_upm_nand *fun;
- struct resource io_res;
+ struct resource *io_res;
const __be32 *prop;
- int rnb_gpio;
int ret;
int size;
int i;
- fun = kzalloc(sizeof(*fun), GFP_KERNEL);
+ fun = devm_kzalloc(&ofdev->dev, sizeof(*fun), GFP_KERNEL);
if (!fun)
return -ENOMEM;
- ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
- if (ret) {
- dev_err(&ofdev->dev, "can't get IO base\n");
- goto err1;
- }
+ io_res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
+ fun->io_base = devm_ioremap_resource(&ofdev->dev, io_res);
+ if (IS_ERR(fun->io_base))
+ return PTR_ERR(fun->io_base);
- ret = fsl_upm_find(io_res.start, &fun->upm);
+ ret = fsl_upm_find(io_res->start, &fun->upm);
if (ret) {
dev_err(&ofdev->dev, "can't find UPM\n");
- goto err1;
+ return ret;
}
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
&size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM address offset\n");
- ret = -EINVAL;
- goto err1;
+ return -EINVAL;
}
fun->upm_addr_offset = *prop;
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM command offset\n");
- ret = -EINVAL;
- goto err1;
+ return -EINVAL;
}
fun->upm_cmd_offset = *prop;
@@ -246,7 +205,7 @@ static int fun_probe(struct platform_device *ofdev)
fun->mchip_count = size / sizeof(uint32_t);
if (fun->mchip_count >= NAND_MAX_CHIPS) {
dev_err(&ofdev->dev, "too much multiple chips\n");
- goto err1;
+ return -EINVAL;
}
for (i = 0; i < fun->mchip_count; i++)
fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
@@ -255,63 +214,26 @@ static int fun_probe(struct platform_device *ofdev)
}
for (i = 0; i < fun->mchip_count; i++) {
- fun->rnb_gpio[i] = -1;
- rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
- if (rnb_gpio >= 0) {
- ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
- if (ret) {
- dev_err(&ofdev->dev,
- "can't request RNB gpio #%d\n", i);
- goto err2;
- }
- gpio_direction_input(rnb_gpio);
- fun->rnb_gpio[i] = rnb_gpio;
- } else if (rnb_gpio == -EINVAL) {
+ fun->rnb_gpio[i] = devm_gpiod_get_index_optional(&ofdev->dev,
+ NULL, i,
+ GPIOD_IN);
+ if (IS_ERR(fun->rnb_gpio[i])) {
dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
- goto err2;
+ return PTR_ERR(fun->rnb_gpio[i]);
}
}
- prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
- if (prop)
- fun->chip_delay = be32_to_cpup(prop);
- else
- fun->chip_delay = 50;
-
- prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
- if (prop && size == sizeof(uint32_t))
- fun->wait_flags = be32_to_cpup(prop);
- else
- fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
- FSL_UPM_WAIT_WRITE_BYTE;
-
- fun->io_base = devm_ioremap(&ofdev->dev, io_res.start,
- resource_size(&io_res));
- if (!fun->io_base) {
- ret = -ENOMEM;
- goto err2;
- }
-
+ nand_controller_init(&fun->base);
+ fun->base.ops = &fun_ops;
fun->dev = &ofdev->dev;
- fun->last_ctrl = NAND_CLE;
- ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
+ ret = fun_chip_init(fun, ofdev->dev.of_node, io_res);
if (ret)
- goto err2;
+ return ret;
dev_set_drvdata(&ofdev->dev, fun);
return 0;
-err2:
- for (i = 0; i < fun->mchip_count; i++) {
- if (fun->rnb_gpio[i] < 0)
- break;
- gpio_free(fun->rnb_gpio[i]);
- }
-err1:
- kfree(fun);
-
- return ret;
}
static int fun_remove(struct platform_device *ofdev)
@@ -319,20 +241,11 @@ static int fun_remove(struct platform_device *ofdev)
struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
struct nand_chip *chip = &fun->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
- int ret, i;
+ int ret;
ret = mtd_device_unregister(mtd);
WARN_ON(ret);
nand_cleanup(chip);
- kfree(mtd->name);
-
- for (i = 0; i < fun->mchip_count; i++) {
- if (fun->rnb_gpio[i] < 0)
- break;
- gpio_free(fun->rnb_gpio[i]);
- }
-
- kfree(fun);
return 0;
}