diff options
Diffstat (limited to 'drivers/tty/serial/8250/8250_uniphier.c')
-rw-r--r-- | drivers/tty/serial/8250/8250_uniphier.c | 62 |
1 files changed, 21 insertions, 41 deletions
diff --git a/drivers/tty/serial/8250/8250_uniphier.c b/drivers/tty/serial/8250/8250_uniphier.c index 28d88ccf5a0c..164ba133437a 100644 --- a/drivers/tty/serial/8250/8250_uniphier.c +++ b/drivers/tty/serial/8250/8250_uniphier.c @@ -12,9 +12,6 @@ #include "8250.h" -/* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */ -#define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64 - /* * This hardware is similar to 8250, but its register map is a bit different: * - MMIO32 (regshift = 2) @@ -158,42 +155,6 @@ static void uniphier_serial_dl_write(struct uart_8250_port *up, int value) writel(value, up->port.membase + UNIPHIER_UART_DLR); } -static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port, - struct uniphier8250_priv *priv) -{ - int ret; - u32 prop; - struct device_node *np = dev->of_node; - - ret = of_alias_get_id(np, "serial"); - if (ret < 0) { - dev_err(dev, "failed to get alias id\n"); - return ret; - } - port->line = ret; - - /* Get clk rate through clk driver */ - priv->clk = devm_clk_get(dev, NULL); - if (IS_ERR(priv->clk)) { - dev_err(dev, "failed to get clock\n"); - return PTR_ERR(priv->clk); - } - - ret = clk_prepare_enable(priv->clk); - if (ret < 0) - return ret; - - port->uartclk = clk_get_rate(priv->clk); - - /* Check for fifo size */ - if (of_property_read_u32(np, "fifo-size", &prop) == 0) - port->fifosize = prop; - else - port->fifosize = UNIPHIER_UART_DEFAULT_FIFO_SIZE; - - return 0; -} - static int uniphier_uart_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -226,10 +187,25 @@ static int uniphier_uart_probe(struct platform_device *pdev) memset(&up, 0, sizeof(up)); - ret = uniphier_of_serial_setup(dev, &up.port, priv); - if (ret < 0) + ret = of_alias_get_id(dev->of_node, "serial"); + if (ret < 0) { + dev_err(dev, "failed to get alias id\n"); + return ret; + } + up.port.line = ret; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(priv->clk); + } + + ret = clk_prepare_enable(priv->clk); + if (ret) return ret; + up.port.uartclk = clk_get_rate(priv->clk); + spin_lock_init(&priv->atomic_write_lock); up.port.dev = dev; @@ -241,10 +217,14 @@ static int uniphier_uart_probe(struct platform_device *pdev) up.port.type = PORT_16550A; up.port.iotype = UPIO_MEM32; + up.port.fifosize = 64; up.port.regshift = UNIPHIER_UART_REGSHIFT; up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE; up.capabilities = UART_CAP_FIFO; + if (of_property_read_bool(dev->of_node, "auto-flow-control")) + up.capabilities |= UART_CAP_AFE; + up.port.serial_in = uniphier_serial_in; up.port.serial_out = uniphier_serial_out; up.dl_read = uniphier_serial_dl_read; |