diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json index 21fe5fe229aa..8d2f4edfb597 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,7 +1,6 @@ [ { "BriefDescription": "BACLEARS asserted.", - "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "2000000", @@ -9,7 +8,6 @@ }, { "BriefDescription": "Cycles during which instruction fetches are stalled.", - "Counter": "0,1", "EventCode": "0x86", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "SampleAfterValue": "2000000", @@ -17,7 +15,6 @@ }, { "BriefDescription": "Decode stall due to IQ full", - "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -25,7 +22,6 @@ }, { "BriefDescription": "Decode stall due to PFB empty", - "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", @@ -33,7 +29,6 @@ }, { "BriefDescription": "Instruction fetches.", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200000", @@ -41,7 +36,6 @@ }, { "BriefDescription": "Icache hit", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200000", @@ -49,7 +43,6 @@ }, { "BriefDescription": "Icache miss", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200000", @@ -57,7 +50,6 @@ }, { "BriefDescription": "All Instructions decoded", - "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.ALL_DECODED", "SampleAfterValue": "2000000", @@ -65,7 +57,6 @@ }, { "BriefDescription": "CISC macro instructions decoded", - "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", @@ -73,7 +64,6 @@ }, { "BriefDescription": "Non-CISC nacro instructions decoded", - "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", @@ -81,7 +71,6 @@ }, { "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", - "Counter": "0,1", "CounterMask": "1", "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", |