diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/icelake/pipeline.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/icelake/pipeline.json | 1114 |
1 files changed, 592 insertions, 522 deletions
diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json index 4f4ce309c2f8..573ac7ac8879 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -1,50 +1,39 @@ [ { - "BriefDescription": "Mispredicted indirect CALL instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", - "SampleAfterValue": "50021", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of uops executed on the core.", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE", + "CounterMask": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops executed from any thread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x9" }, { - "BriefDescription": "Number of uops executed on port 4 and 9", + "BriefDescription": "All branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_4_9", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "BriefDescription": "Conditional branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.THREAD", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x11" }, { "BriefDescription": "Not taken branch instructions retired.", @@ -59,66 +48,64 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", + "BriefDescription": "Taken conditional branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts taken conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "BriefDescription": "Far branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { - "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", "SampleAfterValue": "100003", "UMask": "0x80" }, { - "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "BriefDescription": "Direct and indirect near call instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { - "BriefDescription": "Number of uops executed on port 2 and 3", + "BriefDescription": "Return instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_2_3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { "BriefDescription": "Taken branch instructions retired.", @@ -133,188 +120,192 @@ "UMask": "0x20" }, { - "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "BriefDescription": "All mispredicted branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x4c", - "EventName": "LOAD_HIT_PREFETCH.SWPF", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "50021" }, { - "BriefDescription": "Number of uops executed on port 1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x11" }, { - "BriefDescription": "Number of Uops delivered by the LSD.", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xa8", - "EventName": "LSD.UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "BriefDescription": "Number of uops executed on port 5", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x20" + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x1" }, { - "BriefDescription": "Number of uops executed on port 6", + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_6", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x40" + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "SampleAfterValue": "50021", + "UMask": "0x80" }, { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "BriefDescription": "Mispredicted indirect CALL instructions retired.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "SampleAfterValue": "50021", + "UMask": "0x2" }, { - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "50021", + "UMask": "0x20" }, { - "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", - "SampleAfterValue": "1000003", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x40" + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", "SampleAfterValue": "25003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "500009", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "BriefDescription": "Reference cycles when the core is not in halt state.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", - "SampleAfterValue": "100003", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x3" }, { - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5e", - "EventName": "RS_EVENTS.EMPTY_CYCLES", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "SampleAfterValue": "25003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "BriefDescription": "Core cycles when the thread is not in halt state", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Thread cycles when thread is not in halt state", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "Invert": "1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event counts cycles without actually retired uops.", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts far branch instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x40" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Cycles while memory subsystem has an outstanding load.", @@ -329,160 +320,169 @@ "UMask": "0x10" }, { - "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.ANY", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xc" }, { - "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SCOREBOARD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x5" }, { - "BriefDescription": "Increments whenever there is an update to the LBR array.", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.LBR_INSERTS", + "CounterMask": "20", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", - "SampleAfterValue": "100003", - "UMask": "0x20" + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x14" }, { - "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "BriefDescription": "Total execution stalls.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003" + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Counts the number of x87 uops dispatched.", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of x87 uops executed.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x2" }, { - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x4" }, { - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SB", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", - "SampleAfterValue": "100003", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x8" }, { - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "SampleAfterValue": "100003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x10" }, { - "BriefDescription": "Number of machine clears (nukes) of any type.", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.COUNT", + "CounterMask": "2", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of machine clears (nukes) of any type.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", - "SampleAfterValue": "50021", - "UMask": "0x20" + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "BriefDescription": "Return instructions retired.", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "BriefDescription": "Number of all retired NOP instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x14", - "EventName": "ARITH.DIVIDER_ACTIVE", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x9" + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { "BriefDescription": "Cycles without actually retired instructions.", @@ -499,241 +499,221 @@ "UMask": "0x1" }, { - "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", - "SampleAfterValue": "50021", - "UMask": "0x10" - }, - { - "BriefDescription": "Core cycles when the thread is not in halt state", - "CollectPEBSRecord": "2", - "Counter": "33", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x3" }, { - "BriefDescription": "Taken conditional branch instructions retired.", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x80" }, { - "BriefDescription": "Direct and indirect near call instructions retired.", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x2" + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "BriefDescription": "TMA slots where uops got dropped", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "EventCode": "0x0d", + "EventName": "INT_MISC.UOP_DROPPING", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", - "SampleAfterValue": "2000003", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x10" }, { - "BriefDescription": "Total execution stalls.", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x8" }, { - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xc" + "UMask": "0x2" }, { - "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "BriefDescription": "False dependencies due to partial compare on address.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.PAUSE_INST", - "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", "SampleAfterValue": "100003", - "UMask": "0x40" + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Self-modifying code (SMC) detected.", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.SMC", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Uops that RAT issues to RS", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "5", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_OK", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x5" + "UMask": "0x1" }, { - "BriefDescription": "Reference cycles when the core is not in halt state.", + "BriefDescription": "Number of Uops delivered by the LSD.", "CollectPEBSRecord": "2", - "Counter": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PEBScounters": "34", - "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "0,1,2,3", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x3" + "UMask": "0x1" }, { - "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "BriefDescription": "Number of machine clears (nukes) of any type.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x0D", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x3" + "UMask": "0x1" }, { - "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "BriefDescription": "Self-modifying code (SMC) detected.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" }, { - "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "BriefDescription": "Increments whenever there is an update to the LBR array.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.PAUSE_INST", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", - "SampleAfterValue": "500009", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x8" }, { - "BriefDescription": "Cycles with less than 10 actually retired uops.", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "All branch instructions retired.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "EventCode": "0x5e", + "EventName": "RS_EVENTS.EMPTY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all branch instructions retired.", - "SampleAfterValue": "400009" + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", @@ -751,51 +731,63 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xec", - "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", - "SampleAfterValue": "25003", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Thread cycles when thread is not in halt state", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "SampleAfterValue": "2000003", - "Speculative": "1" + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" }, { - "BriefDescription": "Mispredicted conditional branch instructions retired.", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x11" + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" }, { "BriefDescription": "Number of uops executed on port 0", @@ -810,62 +802,150 @@ "UMask": "0x1" }, { - "BriefDescription": "Conditional branch instructions retired.", + "BriefDescription": "Number of uops executed on port 1", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x11" + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Retirement slots used.", + "BriefDescription": "Number of uops executed on port 2 and 3", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.SLOTS", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_2_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the retirement slots used each cycle.", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of uops executed on port 4 and 9", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of uops executed on port 5", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_5", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of uops executed on port 6", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_6", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of uops executed on port 7 and 8", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa8", - "EventName": "LSD.CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3c", - "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x2" }, { - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" @@ -884,14 +964,14 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", + "CounterMask": "3", "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" @@ -910,126 +990,116 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "BriefDescription": "Counts the number of x87 uops dispatched.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "EventName": "UOPS_EXECUTED.X87", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts the number of x87 uops executed.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x10" }, { - "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "BriefDescription": "Uops that RAT issues to RS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "50021", - "UMask": "0x80" + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "TMA slots where uops got dropped", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.UOP_DROPPING", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x1" }, { - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "20", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x14" + "UMask": "0x2" }, { - "BriefDescription": "Number of uops executed on port 7 and 8", + "BriefDescription": "Retirement slots used.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_7_8", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "PublicDescription": "Counts the retirement slots used each cycle.", "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x80" + "UMask": "0x2" }, { - "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "BriefDescription": "Cycles without actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x1" + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "All mispredicted branch instructions retired.", + "BriefDescription": "Cycles with less than 10 actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "CounterMask": "10", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "SampleAfterValue": "50021" + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "1000003", + "UMask": "0x2" } ]
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