summaryrefslogtreecommitdiff
path: root/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
diff options
context:
space:
mode:
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/ivytown/pipeline.json')
-rw-r--r--tools/perf/pmu-events/arch/x86/ivytown/pipeline.json250
1 files changed, 0 insertions, 250 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
index d89d3f8db190..d1e64e0d683e 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Divide operations executed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@@ -13,8 +11,6 @@
},
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired macro-conditional branches.",
@@ -43,8 +35,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "Speculative and retired direct near calls.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken macro-conditional branches.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired macro-conditional branches.",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
@@ -112,8 +90,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired direct near calls.",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired indirect calls.",
@@ -142,8 +114,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
@@ -161,8 +129,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -171,8 +137,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -181,8 +145,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
@@ -191,8 +153,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -201,8 +161,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -211,8 +169,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -221,8 +177,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -231,8 +185,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -241,8 +193,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -251,8 +201,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "Speculative and retired mispredicted macro conditional branches.",
@@ -261,8 +209,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Mispredicted indirect branches excluding calls and returns.",
@@ -271,8 +217,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
@@ -281,8 +225,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.",
@@ -291,8 +233,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -301,8 +241,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
@@ -311,8 +249,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
@@ -321,8 +257,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -330,8 +264,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -340,8 +272,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -350,8 +280,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -360,8 +288,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -369,8 +295,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -380,8 +304,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -389,8 +311,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -398,16 +318,12 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -417,8 +333,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -426,8 +340,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"UMask": "0x2"
@@ -435,8 +347,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"SampleAfterValue": "2000003",
@@ -444,8 +354,6 @@
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -454,8 +362,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
@@ -463,8 +369,6 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -473,8 +377,6 @@
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +386,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -494,8 +394,6 @@
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -505,8 +403,6 @@
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -516,8 +412,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -526,8 +420,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -537,8 +429,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -547,8 +437,6 @@
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -558,8 +446,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -568,8 +454,6 @@
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -579,8 +463,6 @@
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -589,8 +471,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -599,8 +479,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -609,8 +487,6 @@
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
@@ -619,8 +495,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000003",
@@ -628,16 +502,12 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PublicDescription": "Number of instructions at retirement.",
@@ -645,8 +515,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "2",
@@ -656,8 +524,6 @@
},
{
"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -667,8 +533,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -677,8 +541,6 @@
},
{
"BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x0D",
@@ -688,8 +550,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -698,8 +558,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -708,8 +566,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "False dependencies in MOB due to partial compare on address.",
@@ -718,8 +574,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -728,8 +582,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -738,8 +590,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -749,8 +599,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -760,8 +608,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -769,8 +615,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -780,8 +624,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
@@ -790,8 +632,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Number of self-modifying-code machine clears detected.",
@@ -800,8 +640,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -809,8 +647,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -818,8 +654,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
@@ -827,8 +661,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
@@ -837,8 +669,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
@@ -846,8 +676,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
@@ -855,8 +683,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).",
@@ -865,8 +691,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -875,8 +699,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Cycles the RS is empty for the thread.",
@@ -885,8 +707,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -897,8 +717,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Cycles which a Uop is dispatched on port 0.",
@@ -908,8 +726,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 0.",
@@ -918,8 +734,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Cycles which a Uop is dispatched on port 1.",
@@ -929,8 +743,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 1.",
@@ -939,8 +751,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Cycles which a Uop is dispatched on port 2.",
@@ -950,8 +760,6 @@
{
"AnyThread": "1",
"BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -959,8 +767,6 @@
},
{
"BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Cycles which a Uop is dispatched on port 3.",
@@ -970,8 +776,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
"PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
@@ -980,8 +784,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Cycles which a Uop is dispatched on port 4.",
@@ -991,8 +793,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 4.",
@@ -1001,8 +801,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Cycles which a Uop is dispatched on port 5.",
@@ -1012,8 +810,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
"PublicDescription": "Cycles per core when uops are dispatched to port 5.",
@@ -1022,8 +818,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
@@ -1032,8 +826,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1043,8 +835,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1054,8 +844,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1065,8 +853,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1076,8 +862,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1087,8 +871,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1098,8 +880,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1109,8 +889,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1120,8 +898,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1131,8 +907,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1142,8 +916,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
@@ -1152,8 +924,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
@@ -1163,8 +933,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1175,8 +943,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
@@ -1185,8 +951,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1195,8 +959,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
@@ -1205,8 +967,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1217,8 +977,6 @@
},
{
"BriefDescription": "Retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1228,8 +986,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1239,8 +995,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1249,8 +1003,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1260,8 +1012,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",