diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index 0c3501e6e5a3..6c92b2be2d06 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -1,7 +1,6 @@ [ { "BriefDescription": "DTLB load misses", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -9,7 +8,6 @@ }, { "BriefDescription": "DTLB load miss large page walks", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -17,7 +15,6 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -25,7 +22,6 @@ }, { "BriefDescription": "DTLB second level hit", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -33,7 +29,6 @@ }, { "BriefDescription": "DTLB load miss page walks complete", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -41,7 +36,6 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", - "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -49,7 +43,6 @@ }, { "BriefDescription": "DTLB misses", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -57,7 +50,6 @@ }, { "BriefDescription": "DTLB miss large page walks", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -65,7 +57,6 @@ }, { "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -73,7 +64,6 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -81,7 +71,6 @@ }, { "BriefDescription": "DTLB miss page walks", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -89,7 +78,6 @@ }, { "BriefDescription": "DTLB miss page walk cycles", - "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -97,7 +85,6 @@ }, { "BriefDescription": "Extended Page Table walk cycles", - "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -105,7 +92,6 @@ }, { "BriefDescription": "ITLB flushes", - "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -113,7 +99,6 @@ }, { "BriefDescription": "ITLB miss", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -121,7 +106,6 @@ }, { "BriefDescription": "ITLB miss large page walks", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -129,7 +113,6 @@ }, { "BriefDescription": "ITLB miss page walks", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -137,7 +120,6 @@ }, { "BriefDescription": "ITLB miss page walk cycles", - "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -145,7 +127,6 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", - "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -154,7 +135,6 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", - "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -163,7 +143,6 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", - "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "PEBS": "1", |