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2023-10-13arm64: tegra: Use correct interrupts for Tegra234 TKEThierry Reding1-6/+6
The shared interrupts 0-9 of the TKE are mapped to interrupts 0-9, but shared interrupts 10-15 are mapped to 256-261. Correct the mapping for the final 6 interrupts. This prevents the TKE from requesting the RTC interrupt (along with several GTE and watchdog interrupts). Reported-by: Shubhi Garg <shgarg@nvidia.com> Fixes: 28d860ed02c2 ("arm64: tegra: Enable native timers on Tegra234") Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-13arm64: tegra: Add power-sensors for Tegra234 boardsJon Hunter3-0/+115
Populate the ina219 and ina3221 power-sensors for the various Tegra234 boards. These sensors are located on the Tegra234 module boards and the configuration of some sensors is common across the different Tegra234 modules. Therefore, add any common sensor configurations to appropriate device tree source file so it can be re-used across modules. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Mark Tegra234 SPI as compatible with Tegra114Thierry Reding1-3/+3
According to the bindings, both Tegra210 and Tegra114 compatible strings need to be specified since the version of this hardware block found in Tegra210 is backwards-compatible. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Add dmas and dma-names for Tegra234 UARTEThierry Reding1-0/+2
Commit 940acdac99b2 ("arm64: tegra: Add UARTE device tree node on Tegra234") added the device tree node for the UARTE on Tegra234 but didn't include the "dmas" and "dma-names" properties required for this device when it's used in high-speed mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Use correct format for clocks propertyThierry Reding1-16/+16
phandle and clock specifier pairs should be enclosed in angular brackets. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Remove duplicate nodes on Jetson Orin NXThierry Reding1-13/+0
The SBSA UART and TCU as well as the TCU alias and the stdout-path are configured via the P3768 carrier board DTS include, so the can be removed from the system DTS file. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Add missing current-speed for SBSA UARTThierry Reding2-0/+2
The SBSA UART device tree bindings require a current-speed property that specifies the baud rate configured by the firmware. Add it on Jetson AGX Orin and Jetson Orin Nano/NX. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Add display panel node on SmaugDiogo Ivo1-0/+27
The Google Pixel C has a JDI LPM102A188A display panel, so add a DT node for it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Add backlight node on SmaugDiogo Ivo1-0/+31
The Google Pixel C has a TI LP8557 backlight controller, so add a DT node for it. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Add DSI/CSI regulator on SmaugDiogo Ivo1-0/+8
Add the node for the DSI/CSI regulator in the Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Enable IOMMU for host1x on Tegra132Rayyan Ansari1-0/+2
Add the iommu property to the host1x node to register it with its swgroup. Signed-off-by: Rayyan Ansari <rayyan@ansari.sh> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Fix P3767 QSPI speedBrad Griffis1-1/+1
The QSPI device used on Jetson Orin NX and Nano modules (p3767) is the same as Jetson AGX Orin (p3701) and should have a maximum speed of 102 MHz. Fixes: 13b0aca303e9 ("arm64: tegra: Support Jetson Orin NX") Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-10arm64: tegra: Fix P3767 card detect polarityBrad Griffis1-1/+1
The SD card detect pin is active-low on all Orin Nano and NX SKUs that have an SD card slot. Fixes: 13b0aca303e9 ("arm64: tegra: Support Jetson Orin NX") Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add blank lines for better readabilityThierry Reding1-0/+8
Add a few blank lines to visually separate blocks in the Jetson AGX Orin device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Remove {clock,reset}-names from VIC powergateThierry Reding1-2/+0
According to the device tree bindings, the powergate definition nodes don't contain clock-names and reset-names properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Drop incorrect maxim,disable-etr on SmaugKrzysztof Kozlowski1-1/+0
There is no "maxim,disable-etr" property (but there is maxim,enable-etr), neither in the bindings nor in the Linux driver: tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add SPI device tree nodes for Tegra234Gautham Srinivasan1-0/+57
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers found on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Enable UARTA and UARTE for Orin NanoGautham Srinivasan1-0/+14
Activate UARTA and UARTE functionalities for Orin Nano. - UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX) - UARTE utilizes the M2.E connector Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add UARTE device tree node on Tegra234Gautham Srinivasan1-0/+9
This commit adds the device tree node for UARTE on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Adapt to LP855X bindings changesArtur Weber1-4/+2
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add PCIe and DP 3.3V suppliesShubhi Garg2-0/+29
Add the 3.3V supplies for PCIe C1 controller and Display Port controller for the NVIDIA IGX Orin platform. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add missing reset-names for Tegra HS UARTThierry Reding1-0/+1
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove current-speed for SBSA UARTThierry Reding3-3/+0
The SBSA UART device tree bindings don't define a current-speed property, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: smaug: Remove reg-shift for high-speed UARTThierry Reding1-0/+1
The device tree bindings for the high-speed UART don't define a reg-shift property, so delete it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove dmas and dma-names for debug UARTThierry Reding7-0/+14
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add 35°C trip point for Jetson Orin NX/NanoThierry Reding3-3/+19
It turns out that these devices can get quite hot to the touch with the standard cooling configuration, so add another trip point at 35°C along with a cooling map to help keep the system reasonably cool at very low system load. Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove duplicate PCI nodesThierry Reding1-44/+0
The PCI nodes for Jetson Orin NX are already defined at the carrier board level, so the duplicates can be dropped at the platform level. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Sort PCI nodes correctly on OrinThierry Reding3-108/+108
Recent changes to several Orin boards didn't order some device tree nodes correctly. Resort them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add audio support for IGX OrinMohan Kumar7-2014/+2170
Add audio support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Move the common device-tree nodes to a new file tegra234-p3701.dtsi and use this for Jetson AGX Orin and NVIDIA IGX Orin platforms Signed-off-by: Mohan Kumar <mkumard@nvidia.com> [treding@nvidia.com: properly sort nodes] Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-14arm64: tegra: Update CPU OPP tablesSumit Gupta1-54/+264
Update the CPU OPP table to include all frequencies supported by Tegra234. Different platforms can choose to keep all or few entries based on their power and performance tunings. Signed-off-by: Shao-Chun Kao <shaochunk@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-14arm64: tegra: Fix HSUART for SmaugDiogo Ivo1-0/+1
After commit 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") was applied, the HSUART failed to probe and the following error is seen: serial-tegra 70006300.serial: Couldn't get the reset serial-tegra: probe of 70006300.serial failed with error -2 Commit 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") is correct because the "reset-names" property is not needed for 8250 UARTs. However, the "reset-names" is required for the HSUART and should have been populated as part of commit a63c0cd83720c ("arm64: dts: tegra: smaug: Add Bluetooth node") that enabled the HSUART for the Pixel C. Fix this by populating the "reset-names" property for the HSUART on the Pixel C. Fixes: a63c0cd83720 ("arm64: dts: tegra: smaug: Add Bluetooth node") Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-13arm64: tegra: Fix HSUART for Jetson AGX OrinJon Hunter1-0/+1
After commit 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") was applied, the HSUART failed to probe and the following error is seen: serial-tegra 3100000.serial: Couldn't get the reset serial-tegra: probe of 3100000.serial failed with error -2 Commit 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") is correct because the "reset-names" property is not needed for 8250 UARTs. However, the "reset-names" is required for the HSUART and should have been populated as part of commit ff578db7b693 ("arm64: tegra: Enable UART instance on 40-pin header") that enabled the HSUART for Jetson AGX Orin. Fix this by populating the "reset-names" property for the HSUART on Jetson AGX Orin. Fixes: ff578db7b693 ("arm64: tegra: Enable UART instance on 40-pin header") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-13arm64: tegra: Add missing alias for NVIDIA IGX OrinJon Hunter1-0/+1
The following error is seen on boot for the NVIDIA IGX Orin platform ... serial-tegra 3100000.serial: failed to get alias id, errno -19 Fix this by populating the necessary alias for the serial device. Fixes: c95711d7dbc4 ("arm64: tegra: Add support for IGX Orin") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-13arm64: tegra: Update AHUB clock parent and rateSameer Pujar3-3/+6
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely that similar issues would be seen. Thus update the AHUB clock parent and rates here as well for Tegra194, Tegra186 and Tegra210. Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components") Cc: stable@vger.kernel.org Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-13arm64: tegra: Update AHUB clock parent and rate on Tegra234Sheetal1-1/+2
I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz. This happens because the AHUB clock rate is too low and it shows 9.83MHz on boot. The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O clocks. It is recommended that AHUB clock operates higher than this. Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of PLLA_OUT0 and fix the rate to 81.6MHz. Fixes: dc94a94daa39 ("arm64: tegra: Add audio devices on Tegra234") Cc: stable@vger.kernel.org Signed-off-by: Sheetal <sheetal@nvidia.com> Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Enable thermal support on Jetson Orin NanoThierry Reding1-0/+20
Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Enable thermal support on Jetson Orin NXThierry Reding3-61/+23
Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. This also removes a duplicate definition of the PWM fan and changes its cooling levels. This should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Enable thermal support on Jetson AGX OrinThierry Reding3-5/+45
Add thermal zone details and enable the PWM fan as cooling device. Note that this also changes the cooling levels for the PWM fan, which should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add Tegra234 thermal supportThierry Reding1-0/+53
Add device tree node for the BPMP thermal node on Tegra234 and add thermal zone definitions. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add a few blank lines for better readabilityThierry Reding1-0/+10
Surround device tree nodes with blank lines for increased readability. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Sort properties more logicallyThierry Reding1-2/+1
We typically sort the "compatible" property first because it defines what the remainder of the properties can be. For the sound node on the Jetson AGX Orin this wasn't done, so fix that up. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Enable GPU on SmaugDiogo Ivo1-0/+5
Enable the GPU on the Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add GPU power rail regulator on SmaugDiogo Ivo1-1/+17
Add the GPU power rail regulator node for the Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Update USB phy-name for Jetson Orin NXJon Hunter1-1/+1
Running 'make dtbs_check' reports the following warning for the Jetson Orin NX platform ... arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dtb: usb@3550000: phy-names:1: 'usb3-0' was expected Fix this by updating the phy-names:1 to be 'usb3-0' as expected. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Enable USB device for Jetson AGX OrinJon Hunter1-1/+10
Enable USB device support for the Jetson AGX Orin platform and update the mode for the usb2-0 port to be on-the-go. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Add Tegra234 pin controllersPrathamesh Shete1-0/+12
Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra234 family of SoCs. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Support Jetson Orin Nano Developer KitThierry Reding3-0/+29
The NVIDIA Jetson Orin Nano Developer Kit is the combination of the NVIDIA Jetson Orin Nano (P3767, SKU 5) module and the P3768 carrier board. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-01arm64: tegra: Add missing cache properties on Tegra210Krzysztof Kozlowski1-0/+1
As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: tegra210-p2371-0000.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-26arm64: tegra: Fix PCIe regulator for Orin Jetson AGXJon Hunter1-1/+1
The PCIe slot on the Jetson Orin AGX is not working and PCIe cards are not detected. The regulator for the 3.3V regulator for the PCIe is using the wrong GPIO for turning on the regulator. Fix this by updating the 3.3V regulator to use the correct GPIO. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-16arm64: tegra: Add CPU OPP tables and interconnects propertySumit Gupta1-0/+276
Add OPP table and interconnects property to scale DDR frequency with CPU frequency for better performance. Each operating point entry of the OPP table has CPU freq to per MC channel bandwidth mapping. One table is added for each cluster even though the table data is same because the bandwidth request is per cluster. This is done because OPP framework creates a single icc path and hence single bandwidth request if the table is marked as 'opp-shared' and shared among all clusters. For us, the OPP table data is same but the MC Client ID argument to interconnects property is different for each cluster. So, having per cluster table makes different icc path for each cluster and helps to make per cluster BW requests. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-25 15:56:56 +0300