Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-10-12 | arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache | Claudiu Beznea | 1 | -0/+1 |
2023-10-12 | arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2 | Claudiu Beznea | 1 | -0/+30 |
2023-10-05 | arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC | Claudiu Beznea | 1 | -0/+139 |