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2024-02-19arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodesSuman Anna1-0/+24
The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Link: https://lore.kernel.org/r/20240215103036.2825096-2-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-19arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodesJudith Mendez1-0/+2
Move bus-width property to *main.dtsi, above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if the bus-width property is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing bus-width for MMC2 in k3-am62-main. Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-9-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-19arm64: dts: ti: k3-am6*: Fix ti,clkbuf-sel property in MMC nodesJudith Mendez1-1/+2
Move ti,clkbuf-sel property above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if ti,clkbuf-sel is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing ti,clkbuf-sel for MMC0 in k3-am64-main. Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-8-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-19arm64: dts: ti: k3-am6*: Remove DLL properties for soft PHYsJudith Mendez1-1/+0
Remove DLL properties which are not applicable for soft PHYs since these PHYs do not have a DLL to enable. Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Verdin AM62 Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-7-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-19arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMCJudith Mendez1-1/+8
Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am6442.pdf Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-5-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-14arm64: dts: ti: k3-am64: Convert serdes_ln_ctrl node into reg-muxAndrew Davis1-3/+4
This removes a dependency on the parent node being a syscon node. Convert from mmio-mux to reg-mux adjusting node name and properties as needed. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124184722.150615-1-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-06arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0Nishanth Menon1-2/+2
Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Roger Quadros <rogerq@kernel.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Wadim Egorov <w.egorov@phytec.de> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Roger Quadros <rogerq@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-02-05arm64: dts: ti: k3-am64: Remove PCIe endpoint nodeAndrew Davis1-19/+0
This node is an example node for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240124183659.149119-4-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-12-15arm64: dts: ti: k3-am6*: Add additional regs for DMA componentsVignesh Raghavendra1-4/+14
Add additional reg properties for BCDMA and PKTDMA nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-4-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-04arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board levelAndrew Davis1-0/+2
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-12-01arm64: dts: ti: k3-am64-main: Fix typo in epwm_tbclk node nameAndrew Davis1-1/+1
The node name has @4140 but the reg is at 4130, fix this here. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117162059.88633-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-10-12arm64: dts: ti: k3-*: Convert DMSS to simple-busVignesh Raghavendra1-1/+1
"simple-mfd" as standalone compatible is frowned upon, so model DMSS (Data Movement Subsystem) node as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-2-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-10-02arm64: dts: ti: k3-am64: Fix indentation in watchdog nodesWadim Egorov1-12/+12
Use single instead of double tab. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20230912133036.257277-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-10-02arm64: dts: ti: k3-am64: Add phase tags markingNishanth Menon1-0/+11
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. On TI K3 AM642 SoC, only esm nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. Add bootph-all for all other nodes that are used in the bootloader on K3 AM642 SoC, and bootph-pre-ram is not needed specifically for any other node in kernel dts. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230911172902.1057417-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-08-10arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board levelAndrew Davis1-0/+1
TSCADC nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-14-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-10arm64: dts: ti: k3-am64: Enable OSPI nodes at the board levelAndrew Davis1-0/+1
OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-8-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-05arm64: dts: ti: k3: Fix epwm_tbclk node name to generic nameAndrew Davis1-1/+1
The name "clock" is not allowed for nodes, use "clock-controller" to remove the DTS check warning. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230802174521.236255-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-08-05arm64: dts: ti: k3-am64: Merge the two main_conf nodesAndrew Davis1-25/+17
There are two nodes representing the same register space, this looks to have been created by some merge or copy/paste error. Remove the second instance of this node and move its children into the first instance. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230802174521.236255-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-15arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclkNishanth Menon1-1/+1
TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a syscon compatibility. Fixes the following dtbs_check warnings: compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-11arm64: dts: ti: add missing space before {Krzysztof Kozlowski1-2/+2
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon <nm@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Add ESM supportNishanth Menon1-0/+6
Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Only set UART baud for used portsAndrew Davis1-7/+0
As the binding for "current-speed" states, this should only be used when the baud rate of an attached device cannot be detected. This is the case for our attached on-board USB-to-UART converter used for early kernel console. For all other unconnected/disabled ports this can be configured in userspace later, DT is not the place for device configuration, especially when there are already standard ways to set serial baud in userspace. Remove setting baud for all disabled serial ports and move setting it for the couple enabled ports down into the board files. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board levelAndrew Davis1-0/+6
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-am64-main: add VTM nodeBryan Brattlof1-0/+8
The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-2-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am64: Add general purpose timersNishanth Menon1-0/+144
There are 11 general purpose timers on am64 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am65, the timers on am64 do not have a dedicated IO mux for the timers. On am62, the timers have different interrupts, clocks and power domains compared to am65, and the MCU timers are at a different IO address. Compared to AM62, the AM64 times have different clocks and count in main domain are different as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-11-17arm64: dts: ti: k3-am64-main: Drop RNG clockJayesh Choudhary1-1/+0
The x1-clk used by trng submodule comes directly from the system clock after a fixed divider. It is always running and has a fixed frequency that cannot be changed, making it uncontrollable. Hence this property should be dropped from the rng node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221107110607.59216-4-j-choudhary@ti.com
2022-11-15arm64: dts: ti: Trim addresses to 8 digitsKrzysztof Kozlowski1-2/+2
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115105044.95225-1-krzysztof.kozlowski@linaro.org
2022-11-03arm64: dts: ti: Rename clock-names adc_tsc_fck to fckMatt Ranostay1-1/+1
Avoid the following warnings from dt-schema by just renaming the clock-names string from adc_tsc_fck to fck so it matches the values in ti,am3359-tscadc.yaml tscadc@40200000: clock-names:0: 'fck' was expected Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Judith Mendez <jm@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221024151648.394623-1-mranostay@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable GPMC and ELM nodes at the board levelAndrew Davis1-0/+2
The GPMC node defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless it is extended with pinmux information. As the pinmux is only known at the board integration level, this node should only be enabled when provided with this information. Disable the GPMC node in the dtsi file. Since the ELM is made to work with the GPMC, disable it too. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-11-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable MCAN nodes at the board levelAndrew Davis1-0/+2
MCAN nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-10-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable MDIO nodes at the board levelAndrew Davis1-0/+3
MDIO nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes (in both CPSW and ICSSG) in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-9-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable PCIe nodes at the board levelAndrew Davis1-0/+2
PCIe nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-7-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable ECAP nodes at the board levelAndrew Davis1-0/+3
ECAP nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. (These and the EPWM nodes could be used to trigger internal actions but they are not used like that currently) As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the ECAP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-6-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable EPWM nodes at the board levelAndrew Davis1-0/+9
EPWM nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the EPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-5-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable SPI nodes at the board levelAndrew Davis1-0/+5
SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-4-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable I2C nodes at the board levelAndrew Davis1-0/+4
I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-3-afd@ti.com
2022-10-28arm64: dts: ti: k3-am64: Enable UART nodes at the board levelAndrew Davis1-0/+7
UART nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221017192532.23825-2-afd@ti.com
2022-09-01arm64: dts: ti: k3-am64-main: Add ELM (Error Location Module) nodeRoger Quadros1-0/+9
The ELM module is used for GPMC NAND accesses for detecting and correcting errors during reads due to NAND bitflips errors. 4-, 8-, and 16-bit error-correction levels are supported using the BCH (Bose-ChaudhurI-Hocquenghem) algorithm. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220802104456.11069-3-rogerq@kernel.org
2022-09-01arm64: dts: ti: k3-am64-main: Add GPMC memory controller nodeRoger Quadros1-0/+19
The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220802104456.11069-2-rogerq@kernel.org
2022-09-01arm64: dts: ti: k3-am64-main: Enable crypto acceleratorPeter Ujfalusi1-0/+20
Add the node for SA2UL. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [s-anna@ti.com: drop label, minor cleanups] Signed-off-by: Suman Anna <s-anna@ti.com> [j-choudhary@ti.com: disable rng-node, change flag to shared] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20220711085743.10128-3-j-choudhary@ti.com
2022-09-01arm64: dts: ti: k3-am64-main: Add main_cpts labelChristian Gmeiner1-1/+1
Makes it easier to reference the node in board dts files. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220822095943.18563-1-christian.gmeiner@gmail.com
2022-06-18arm64: dts: ti: Adjust whitespace around '='Krzysztof Kozlowski1-2/+2
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
2022-06-18arm64: dts: ti: k3-am64-main: Remove support for HS400 speed modeAswath Govindraju1-2/+0
AM64 SoC, does not support HS400 and HS200 is the maximum supported speed mode[1]. Therefore, fix the device tree node to reflect the same. [1] - https://www.ti.com/lit/ds/symlink/am6442.pdf (SPRSP56C – JANUARY 2021 – REVISED FEBRUARY 2022) Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220512064859.32059-1-a-govindraju@ti.com
2022-02-22arm64: dts: ti: k3-am64: Fix gic-v3 compatible regsNishanth Menon1-1/+4
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com
2022-02-04arm64: dts: ti: k3-am64-main: Add RTI watchdog nodesChristian Gmeiner1-0/+18
Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-By: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20220111134552.800704-1-christian.gmeiner@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2021-12-07arm64: dts: ti: k3-am64-main: Add support for MCANAswath Govindraju1-0/+28
Add Support for two MCAN controllers present on the am64x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-6-a-govindraju@ti.com
2021-12-03arm64: dts: ti: k3-am64-main: add timesync router nodeChristian Gmeiner1-0/+8
The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of multiplexers to provide selection of active CPTS time sync events for routing to CPTS capable modules. This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211202173114.9936-1-christian.gmeiner@gmail.com
2021-10-06arm64: dts: ti: k3-am64-main: Add ICSSG nodesSuman Anna1-0/+280
Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are present on the K3 AM64x SoCs. The two ICSSGs are identical to each other for the most part, with some of the peripheral pins from ICSSG1 not pinned out. Each ICSSG instance is represented by a PRUSS subsystem node and other child nodes. The nodes are all added and enabled in the common k3-am64-main.dtsi file by default. The MDIO nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. These are disabled in the existing AM64x board dts files to begin with. The ICSSGs on K3 AM64x SoCs are very similar to the versions of the ICSSG on K3 J721E and AM65x SR2.0 SoCs. The IRAM and BroadSize RAM sizes are all identical to those on J721E SoCs. All The ICSSG host interrupts intended towards the main Arm core are also shared with other processors on the SoC, and can be partitioned as per system integration needs. The ICSSG subsystem node contains the entire address space. The various sub-modules of the ICSSG are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include: - two Programmable Real-Time Units (PRUs) - two auxiliary PRU cores called RTUs - two Transmit Programmable Real-Time Units (Tx_PRUs) - Interrupt controller (INTC) - a 'memories' node containing all the ICSSG level Data RAMs - Real Time Media Independent Interface controller (MII_RT) - Gigabit capable MII_G_RT - ICSSG CFG sub-module providing two internal clock muxes, with the default clock parents also assigned using the assigned-clock-parents property. The default names for the firmware images for each PRU, RTU and Tx_PRU cores are defined as follows using the 'firmware-name' property (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): ICSSG0 PRU0 Core : am64x-pru0_0-fw ; PRU1 Core : am64x-pru0_1-fw ICSSG0 RTU0 Core : am64x-rtu0_0-fw ; RTU1 Core : am64x-rtu0_1-fw ICSSG0 Tx_PRU0 Core : am64x-txpru0_0-fw ; Tx_PRU1 Core : am64x-txpru0_1-fw ICSSG1 PRU0 Core : am64x-pru1_0-fw ; PRU1 Core : am64x-pru1_1-fw ICSSG1 RTU0 Core : am64x-rtu1_0-fw ; RTU1 Core : am64x-rtu1_1-fw ICSSG1 Tx_PRU0 Core : am64x-txpru1_0-fw ; Tx_PRU1 Core : am64x-txpru1_1-fw Note: 1. The ICSSG INTC on AM64x SoCs share all the host interrupts with other processors, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. 2. There are few more sub-modules like the Industrial Ethernet Peripherals (IEPs), eCAP, PWM, UART that do not have bindings and so will be added in the future. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210919202935.15604-1-s-anna@ti.com
2021-07-30arm64: dts: ti: k3-am64-main: Add ecap pwm nodesLokesh Vutla1-0/+27
There are 3 instances of ecap modules that are capable of generating a pwm when configured in apwm mode. Add DT nodes for these 3 ecap instances. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20210721113625.17299-3-lokeshvutla@ti.com
2021-07-30arm64: dts: ti: k3-am64-main: Add epwm nodesLokesh Vutla1-0/+87
Add DT nodes for all epwm instances present in AM64 SoC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20210721113625.17299-2-lokeshvutla@ti.com
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