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path: root/arch/riscv/errata/thead
AgeCommit message (Expand)AuthorFilesLines
2023-07-06riscv: errata: thead: only set cbom size & noncoherent during bootJisheng Zhang1-2/+5
2023-04-29RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap1-3/+3
2023-04-26RISC-V: hwprobe: Remove __init on probe_vendor_features()Evan Green1-3/+3
2023-04-19Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt1-0/+10
2023-04-19RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green1-0/+10
2023-03-15riscv: alternatives: Rename errata_id to patch_idAndrew Jones1-2/+2
2023-02-22RISC-V: take text_mutex during alternative patchingConor Dooley1-2/+6
2023-02-15riscv: Fix early alternative patchingSamuel Holland1-3/+1
2023-02-01riscv: switch to relative alternative entriesJisheng Zhang1-3/+8
2022-10-28drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx coresHeiko Stuebner1-0/+19
2022-10-13Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt1-6/+8
2022-10-13riscv: check for kernel config option in t-head memory types errataHeiko Stuebner1-0/+3
2022-10-13riscv: use BIT() macros in t-head errata initHeiko Stuebner1-2/+2
2022-10-13riscv: drop some idefs from CMO initializationHeiko Stuebner1-4/+3
2022-09-13RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt1-0/+1
2022-08-04riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner1-0/+20
2022-06-17riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner1-26/+12
2022-05-12riscv: add memory-type errata for T-HeadHeiko Stuebner2-0/+93