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path: root/arch/riscv/errata
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2023-07-06Merge patch series "riscv: some CMO alternative related clean up"Palmer Dabbelt1-2/+5
2023-07-06riscv: errata: thead: only set cbom size & noncoherent during bootJisheng Zhang1-2/+5
2023-05-31riscv: Fix relocatable kernels with early alternatives using -fno-pieAlexandre Ghiti1-0/+4
2023-04-29RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap2-8/+6
2023-04-29Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2-6/+16
2023-04-26RISC-V: hwprobe: Remove __init on probe_vendor_features()Evan Green1-3/+3
2023-04-19Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt1-0/+10
2023-04-19RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green1-0/+10
2023-03-15riscv: alternatives: Rename errata_id to patch_idAndrew Jones2-5/+5
2023-03-15riscv: alternatives: Remove unnecessary define and unused structAndrew Jones1-1/+1
2023-03-07RISC-V: fix taking the text_mutex twice during sifive errata patchingConor Dooley1-1/+1
2023-02-22RISC-V: take text_mutex during alternative patchingConor Dooley2-2/+9
2023-02-15riscv: Fix early alternative patchingSamuel Holland1-3/+1
2023-02-01riscv: switch to relative alternative entriesJisheng Zhang2-4/+10
2022-10-28drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx coresHeiko Stuebner1-0/+19
2022-10-13Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt1-6/+8
2022-10-13riscv: check for kernel config option in t-head memory types errataHeiko Stuebner1-0/+3
2022-10-13riscv: use BIT() macros in t-head errata initHeiko Stuebner1-2/+2
2022-10-13riscv: drop some idefs from CMO initializationHeiko Stuebner1-4/+3
2022-09-13RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt1-0/+1
2022-08-11riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt1-0/+20
2022-08-07Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-26/+12
2022-08-04riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner1-0/+20
2022-07-08riscv: don't warn for sifive erratas in modulesHeiko Stuebner1-1/+2
2022-06-17riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner1-26/+12
2022-05-12riscv: add memory-type errata for T-HeadHeiko Stuebner4-1/+100
2022-05-12riscv: implement module alternativesHeiko Stuebner1-5/+9
2022-05-12riscv: allow different stages with alternativesHeiko Stuebner1-1/+2
2022-05-12riscv: integrate alternatives better into the main architectureHeiko Stuebner2-76/+0
2022-01-09riscv: errata: alternative: mark vendor_patch_func __initdataJisheng Zhang1-1/+2
2021-06-02riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent1-1/+1
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen1-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen3-0/+59
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen4-0/+75
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2-0/+70