| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-05-22 | riscv: cpufeature: Fix thead vector hwcap removal | Charlie Jenkins | 1 | -4/+36 |
| 2023-11-09 | Merge patch series "Linux RISC-V AIA Preparatory Series" | Palmer Dabbelt | 1 | -5/+6 |
| 2023-11-09 | RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs | Anup Patel | 1 | -5/+6 |
| 2023-11-08 | RISC-V: Show accurate per-hart isa in /proc/cpuinfo | Evan Green | 1 | -4/+18 |
| 2023-09-01 | Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 1 | -118/+63 |
| 2023-08-09 | riscv: Fix CPU feature detection with SMP disabled | Samuel Holland | 1 | -0/+5 |
| 2023-08-02 | RISC-V: cpu: refactor deprecated strncpy | Justin Stitt | 1 | -6/+6 |
| 2023-07-26 | RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" | Conor Dooley | 1 | -1/+7 |
| 2023-07-26 | RISC-V: try new extension properties in of_early_processor_hartid() | Conor Dooley | 1 | -1/+28 |
| 2023-07-26 | RISC-V: add single letter extensions to riscv_isa_ext | Conor Dooley | 1 | -26/+11 |
| 2023-07-26 | RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() | Conor Dooley | 1 | -2/+3 |
| 2023-07-26 | RISC-V: shunt isa_ext_arr to cpufeature.c | Conor Dooley | 1 | -73/+2 |
| 2023-07-26 | RISC-V: drop a needless check in print_isa_ext() | Conor Dooley | 1 | -4/+0 |
| 2023-07-26 | RISC-V: don't parse dt/acpi isa string to get rv32/rv64 | Heiko Stuebner | 1 | -12/+9 |
| 2023-07-26 | RISC-V: Provide a more helpful error message on invalid ISA strings | Palmer Dabbelt | 1 | -2/+6 |
| 2023-06-23 | Merge patch series "ISA string parser cleanups" | Palmer Dabbelt | 1 | -4/+30 |
| 2023-06-21 | RISC-V: always report presence of extensions formerly part of the base ISA | Conor Dooley | 1 | -0/+4 |
| 2023-06-21 | RISC-V: validate riscv,isa at boot, not during ISA string parsing | Conor Dooley | 1 | -3/+5 |
| 2023-06-21 | RISC-V: split early & late of_node to hartid mapping | Conor Dooley | 1 | -1/+21 |
| 2023-06-20 | Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe" | Palmer Dabbelt | 1 | -0/+2 |
| 2023-06-19 | RISC-V: Add Zba, Zbs extension probing | Evan Green | 1 | -0/+2 |
| 2023-06-07 | Merge patch series "riscv: allow case-insensitive ISA string parsing" | Palmer Dabbelt | 1 | -1/+2 |
| 2023-06-07 | riscv: allow case-insensitive ISA string parsing | Yangyu Chen | 1 | -1/+2 |
| 2023-06-01 | RISC-V: cpu: Enable cpuinfo for ACPI systems | Sunil V L | 1 | -8/+22 |
| 2023-05-05 | Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEAD | Paolo Bonzini | 1 | -0/+2 |
| 2023-04-21 | RISC-V: Detect AIA CSRs from ISA string | Anup Patel | 1 | -0/+2 |
| 2023-04-19 | Merge patch series "RISC-V Hardware Probing User Interface" | Palmer Dabbelt | 1 | -6/+2 |
| 2023-04-19 | RISC-V: Move struct riscv_cpuinfo to new header | Evan Green | 1 | -6/+2 |
| 2023-03-15 | Merge patch series "RISC-V: Apply Zicboz to clear_page" | Palmer Dabbelt | 1 | -0/+1 |
| 2023-03-15 | RISC-V: Add Zicboz detection and block size parsing | Andrew Jones | 1 | -0/+1 |
| 2023-03-10 | Merge patch series "riscv, mm: detect svnapot cpu support at runtime" | Palmer Dabbelt | 1 | -0/+1 |
| 2023-03-08 | riscv: mm: modify pte format for Svnapot | Qinglin Pan | 1 | -0/+1 |
| 2023-02-22 | RISC-V: fix ordering of Zbb extension | Heiko Stuebner | 1 | -1/+1 |
| 2023-01-31 | RISC-V: add zbb support to string functions | Heiko Stuebner | 1 | -0/+1 |
| 2023-01-20 | Merge patch series "Putting some basic order on isa extension lists" | Palmer Dabbelt | 1 | -15/+38 |
| 2023-01-18 | RISC-V: resort all extensions in consistent orders | Conor Dooley | 1 | -2/+2 |
| 2023-01-18 | RISC-V: clarify ISA string ordering rules in cpu.c | Conor Dooley | 1 | -13/+36 |
| 2022-12-15 | Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 1 | -3/+27 |
| 2022-10-28 | RISC-V: Fix /proc/cpuinfo cpumask warning | Andrew Jones | 1 | -0/+3 |
| 2022-10-28 | RISC-V: Cache SBI vendor values | Heiko Stuebner | 1 | -3/+27 |
| 2022-10-14 | Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 1 | -0/+51 |
| 2022-10-14 | RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output | Palmer Dabbelt | 1 | -0/+51 |
| 2022-10-12 | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm | Linus Torvalds | 1 | -0/+1 |
| 2022-10-07 | RISC-V: Print SSTC in canonical order | Palmer Dabbelt | 1 | -1/+1 |
| 2022-10-04 | RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output | Anup Patel | 1 | -0/+51 |
| 2022-10-02 | RISC-V: Probe Svinval extension form ISA string | Mayuresh Chitale | 1 | -0/+1 |
| 2022-08-12 | RISC-V: Add Sstc extension support | Palmer Dabbelt | 1 | -0/+1 |
| 2022-08-12 | RISC-V: Enable sstc extension parsing from DT | Atish Patra | 1 | -0/+1 |
| 2022-08-11 | arch/riscv: add Zihintpause support | Dao Lu | 1 | -0/+1 |
| 2022-08-11 | riscv: implement Zicbom-based CMO instructions + the t-head variant | Palmer Dabbelt | 1 | -0/+1 |
