summaryrefslogtreecommitdiff
path: root/arch/riscv/mm/context.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-30Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"Palmer Dabbelt1-13/+10
2024-04-30Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ...Palmer Dabbelt1-8/+11
2024-04-29riscv: mm: Preserve global TLB entries when switching contextsSamuel Holland1-1/+1
2024-04-29riscv: mm: Make asid_bits a local variableSamuel Holland1-2/+1
2024-04-29riscv: mm: Use a fixed layout for the MM context IDSamuel Holland1-4/+2
2024-04-29riscv: mm: Introduce cntx2asid/cntx2version helper macrosSamuel Holland1-6/+6
2024-04-18riscv: Include riscv_set_icache_flush_ctx prctlCharlie Jenkins1-8/+11
2024-02-15membarrier: riscv: Add full memory barrier in switch_mm()Andrea Parri1-0/+2
2023-08-31riscv: mm: use bitmap_zero() APIYe Xingchen1-1/+1
2023-03-22riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong1-1/+1
2023-03-10riscv: asid: Fixup stale TLB entry cause application crashGuo Ren1-10/+20
2023-03-10Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich1-10/+0
2022-12-09riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich1-0/+10
2022-01-20riscv: Implement sv48 supportAlexandre Ghiti1-2/+2
2021-10-05riscv: mm: don't advertise 1 num_asid for 0 asid bitsVineet Gupta1-3/+5
2021-07-01riscv: add ASID-based tlbflushing methodsGuo Ren1-1/+1
2021-06-09riscv: mm: Use better bitmap_zalloc()Kefeng Wang1-2/+1
2021-05-29riscv: Add __init section marker to some functions againJisheng Zhang1-1/+1
2021-05-26riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred()Jisheng Zhang1-3/+4
2021-02-19RISC-V: Implement ASID allocatorAnup Patel1-4/+261
2019-11-18riscv: add nommu supportChristoph Hellwig1-0/+2
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng1-6/+1
2019-05-17riscv: move switch_mm to its own fileGary Guo1-0/+69