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path: root/drivers/clk/hisilicon
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2018-04-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds6-38/+232
2018-03-20clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()Wei Yongjun1-0/+2
2018-03-17clk: hisilicon: mark wdt_mux_p[] as constArnd Bergmann1-1/+1
2018-03-15clk: hisilicon: Mark phase_ops staticStephen Boyd1-1/+1
2018-03-13clk: hisilicon: hi3660:Fix potential NULL dereference in hi3660_stub_clk_pr...Wei Yongjun1-0/+2
2018-03-12clk: hi3798cv200: add emmc sample and drive clocktianshuliang1-0/+20
2018-03-12clk: hisilicon: add hisi phase clock supporttianshuliang4-1/+165
2018-02-27clk: hi3798cv200: add COMBPHY0 clock supportJianguo Sun1-4/+11
2018-02-27clk: hi3798cv200: fix define indentationShawn Guo1-24/+24
2018-02-27clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLKShawn Guo1-0/+2
2018-02-27clk: hi3798cv200: correct IR clock parentYounian Wang1-1/+1
2018-02-27clk: hi3798cv200: fix unregister call sequence in error pathShawn Guo1-7/+6
2018-01-27Merge branch 'clk-divider-container' into clk-nextStephen Boyd1-1/+1
2017-12-29clk: divider: fix incorrect usage of container_ofJerome Brunet1-1/+1
2017-12-07clk: hisilicon: Add support for Hi3660 stub clocksKaihua Zhong3-0/+192
2017-11-18Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds6-10/+18
2017-11-14Merge branch 'clk-const' into clk-nextStephen Boyd3-4/+4
2017-11-14clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'Shawn Guo1-1/+11
2017-11-14clk: hisilicon: Delete an error message for a failed memory allocation in his...Markus Elfring1-3/+1
2017-11-14clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua1-1/+1
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2017-11-02clk: hisilicon: make clk_ops constBhumika Goyal3-4/+4
2017-11-01clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan1-1/+1
2017-09-01clk: hi6220: change watchdog clock sourceLeo Yan1-3/+3
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue1-0/+21
2017-06-20clk: hi6220: add acpu clockZhangfei Gao1-0/+22
2017-06-20clk: hi3660: Set PPLL2 to 2880MZhong Kaihua1-2/+2
2017-06-20clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun1-0/+40
2017-06-20clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun1-2/+4
2017-06-20clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan1-10/+38
2017-04-19clk: hi3620: Fix a typo in one variable nameMarkus Elfring1-3/+3
2017-04-19clk: hi3620: Delete error messages for a failed memory allocation in two func...Markus Elfring1-6/+2
2017-04-19clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()Markus Elfring1-1/+1
2017-04-19clk: hisilicon: Delete error messages for failed memory allocations in hisi_c...Markus Elfring1-6/+4
2017-04-19clk: hisilicon: Use devm_kmalloc_array() in hisi_clk_alloc()Markus Elfring1-2/+3
2017-04-19clk: hisilicon: Use kcalloc() in hisi_clk_init()Markus Elfring1-2/+1
2017-04-12clk: hi6220: add debug APB clockLeo Yan1-0/+1
2017-01-27clk: hisilicon: fix lock assignmentLeo Yan1-0/+1
2017-01-10clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao3-0/+575
2016-11-15clk: Hi6220: enable stub clock driver for ARCH_HISILeo Yan1-0/+1
2016-11-15Merge branch 'clk-hisi' into clk-nextStephen Boyd5-0/+719
2016-11-14clk: hisilicon: add CRG driver for Hi3516CV300 SoCPan Wen3-0/+339
2016-11-12clk: hisilicon: add CRG driver for Hi3798CV200 SoCJiancheng Xue4-0/+380
2016-10-18clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock initShawn Guo1-2/+2
2016-07-07clk: hi6220: Change syspll and media_syspll clk to 1.19GHzXinliang Liu1-2/+2
2016-06-30clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue1-16/+100
2016-06-30clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue1-0/+21
2016-06-30clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2-15/+55
2016-06-30clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2-0/+32
2016-06-30reset: hisilicon: change the definition of hisi_reset_initJiancheng Xue3-13/+13