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path: root/drivers/clk/ingenic/jz4725b-cgu.c
AgeCommit message (Expand)AuthorFilesLines
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald1-0/+10
2022-02-18clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau1-2/+1
2021-11-12dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil1-1/+1
2021-06-28clk: Support bypassing dividersPaul Cercueil1-6/+6
2020-05-29clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)1-0/+4
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil1-1/+1
2019-06-26clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil1-0/+3
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-04-11clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil1-0/+6
2018-10-17clk: Add Ingenic jz4725b CGU driverPaul Cercueil1-0/+225