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path: root/drivers/clk/ingenic
AgeCommit message (Expand)AuthorFilesLines
2018-01-19clk: Add Ingenic jz4770 CGU driverPaul Cercueil2-0/+484
2018-01-19clk: ingenic: Add code to enable/disable PLLsPaul Cercueil1-15/+74
2018-01-19clk: ingenic: support PLLs with no bypass bitPaul Cercueil2-1/+4
2018-01-19clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil1-0/+2
2018-01-19clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil2-2/+2
2017-11-03Update MIPS email addressesPaul Burton4-4/+4
2016-05-13clk: ingenic: Allow divider value to be dividedHarvey Hunt4-34/+47
2015-07-20clk: ingenic: Include clk.hStephen Boyd1-0/+1
2015-06-21clk: ingenic: add JZ4780 CGU supportPaul Burton2-0/+734
2015-06-21MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cguPaul Burton1-0/+37
2015-06-21MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cguPaul Burton1-0/+22
2015-06-21MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cguPaul Burton1-0/+22
2015-06-21MIPS,clk: migrate JZ4740 to common clock frameworkPaul Burton2-0/+223
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton3-0/+935