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path: root/drivers/clk/mediatek/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2016-11-09clk: mediatek: Add MT2701 clock supportShunli Wang1-0/+1
2016-08-19clk: mediatek: remove __init from clk registration functionsJames Liao1-1/+1
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-6/+1
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao1-3/+15
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao1-2/+2
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao1-9/+12
2015-05-20clk: mediatek: Initialize clk_init_dataRicky Liang1-1/+1
2015-05-06clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao1-0/+332