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path: root/drivers/clk/meson/axg.c
AgeCommit message (Expand)AuthorFilesLines
2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel1-3/+0
2020-11-23clk: meson: enable building as modulesKevin Hilman1-1/+4
2020-11-23clk: meson: axg: add MIPI DSI Host clockNeil Armstrong1-0/+66
2020-11-23clk: meson: axg: add Video ClocksNeil Armstrong1-0/+753
2019-07-29clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat1-0/+3
2019-07-29clk: meson: axg: migrate to the new parent description methodAlexandre Mergnat1-60/+144
2019-05-20clk: meson: axg: spread spectrum is on mpll2Jerome Brunet1-5/+5
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet1-49/+10
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-1/+4
2019-01-18clk: meson: axg: claim clock controller input clock from DTJerome Brunet1-8/+19
2018-11-08clk: meson: axg: mark fdiv2 and fdiv3 as criticalJerome Brunet1-0/+13
2018-09-26clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan1-2/+4
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet1-37/+36
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-130/+154
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet1-1/+0
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet1-3/+25
2018-07-09clk: meson: add gen_clkJerome Brunet1-1/+63
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan1-0/+145
2018-07-09clk: meson: remove obsolete register accessJerome Brunet1-35/+2
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet1-0/+4
2018-03-15clk: meson: Drop unused local variable and add staticStephen Boyd1-2/+2
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet1-10/+85
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet1-4/+20
2018-03-13clk: meson: axg: add hifi pll clockJerome Brunet1-0/+55
2018-03-13clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet1-1/+6
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet1-1/+0
2018-03-13clk: meson: poke pll CNTL lastJerome Brunet1-1/+1
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet1-13/+30
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-28/+72
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet1-105/+108
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet1-124/+121
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet1-35/+25
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet1-35/+26
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet1-37/+35
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet1-1/+14
2018-03-13clk: meson: remove obsolete commentsJerome Brunet1-5/+0
2018-03-13clk: meson: only one loop index is necessary in probeJerome Brunet1-4/+4
2018-03-13clk: meson: use devm_of_clk_add_hw_providerJerome Brunet1-2/+2
2018-03-13clk: meson: use dev pointer where possibleJerome Brunet1-4/+4
2018-02-12clk: meson: add axg misc bit to the mpll driverJerome Brunet1-0/+20
2018-02-12clk: meson: axg: fix the od shift of the sys_pllYixun Lan1-1/+1
2018-02-12clk: meson: axg: add the fractional part of the fixed_pllJerome Brunet1-0/+5
2018-02-12clk: meson: remove useless pll rate params tablesJerome Brunet1-94/+0
2018-01-11clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)1-0/+2
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)1-1/+1
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)1-1/+1
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai1-0/+936