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path: root/drivers/clk/meson/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2021-05-19clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl1-11/+15
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl1-2/+3
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl1-1/+2
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2020-02-01Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd1-0/+9
2019-12-24clk: let init callback return an error codeJerome Brunet1-1/+3
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel1-0/+9
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd1-0/+26
2019-04-01clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong1-0/+26
2019-03-25clk: meson: pll: fix rounding and setting a rate that matches preciselyMartin Blumenstingl1-1/+1
2019-02-04clk: meson: pll: update driver for the g12aJerome Brunet1-57/+146
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-4/+9
2018-11-23clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl1-0/+19
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet1-23/+46
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-27/+13
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet1-5/+42
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet1-12/+1
2018-03-13clk: meson: add ROUND_CLOSEST to the pll driverJerome Brunet1-4/+13
2018-03-13clk: meson: improve pll driver results with fracJerome Brunet1-47/+90
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet1-11/+1
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet1-150/+93
2018-02-12clk: meson: fix rate calculation of plls with a fractional partJerome Brunet1-1/+0
2018-02-12clk: meson: add od3 to the pll driverJerome Brunet1-3/+16
2018-02-12clk: meson: use the frac parameter width instead of a constantJerome Brunet1-1/+1
2018-02-12clk: meson: remove unnecessary rounding in the pll clockJerome Brunet1-8/+9
2018-02-12clk: meson: check pll rate param table before using itJerome Brunet1-0/+10
2017-04-04clk: meson: Add support for parameters for specific PLLsNeil Armstrong1-2/+51
2016-06-23clk: meson: fractional pll supportMichael Turquette1-2/+30
2016-06-23clk: meson8b: clean up pll clocksMichael Turquette1-61/+11
2015-06-06clk: meson: Add support for Meson clock controllerCarlo Caione1-0/+227