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path: root/drivers/clk/renesas/r9a07g043-cpg.c
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2022-07-05clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar1-0/+32
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy1-0/+2
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy1-12/+6
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy1-2/+1
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy1-6/+4
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das1-0/+9
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das1-0/+18
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das1-0/+10
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das1-0/+9
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das1-0/+5
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das1-0/+12
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das1-0/+12
2022-04-13clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das1-0/+35
2022-04-13clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das1-0/+10
2022-04-13clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das1-0/+13
2022-04-13clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das1-0/+5
2022-04-13clk: renesas: Add support for RZ/G2UL SoCBiju Das1-0/+157