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path: root/drivers/clk/renesas/rzg2l-cpg.h
AgeCommit message (Expand)AuthorFilesLines
2022-10-28clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PMLad Prabhakar1-0/+4
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy1-0/+1
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy1-2/+8
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy1-0/+3
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy1-4/+5
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy1-0/+9
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy1-7/+9
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das1-0/+11
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das1-0/+10
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das1-0/+23
2022-04-13clk: renesas: Add support for RZ/G2UL SoCBiju Das1-0/+1
2022-02-10clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das1-0/+1
2021-12-08clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das1-0/+4
2021-11-19clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das1-0/+2
2021-11-15clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven1-0/+3
2021-10-08clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das1-0/+4
2021-10-08clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das1-0/+12
2021-10-08clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar1-0/+3
2021-09-24clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das1-1/+10
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das1-0/+3
2021-09-24clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das1-0/+12
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven1-0/+155