summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2023-12-13clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1Claudiu Beznea1-0/+10
2023-12-13clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea1-15/+44
2023-12-13clk: renesas: r9a08g045: Add IA55 pclk and its resetClaudiu Beznea1-0/+3
2023-11-27clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea1-23/+15
2023-11-20clk: renesas: r8a779g0: Add PCIe clocksYoshihiro Shimoda1-0/+2
2023-11-20clk: renesas: r8a779g0: Add EtherTSN clockNiklas Söderlund1-0/+1
2023-10-12clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2Claudiu Beznea1-0/+34
2023-10-12clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea1-1/+1
2023-10-10clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea5-1/+228
2023-10-10clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea2-0/+197
2023-10-10clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea4-51/+139
2023-10-05clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea3-4/+14
2023-10-05clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea1-18/+34
2023-10-05clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea2-4/+48
2023-10-05clk: renesas: rzg2l: Remove critical areaClaudiu Beznea1-4/+1
2023-10-05clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea1-6/+6
2023-10-05clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea1-7/+1
2023-10-05clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2-11/+14
2023-10-05clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea1-7/+10
2023-10-05clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme1-1/+14
2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut1-2/+2
2023-09-18clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen1-30/+33
2023-09-18clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen1-0/+1
2023-09-18clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea1-2/+2
2023-09-18clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea1-5/+5
2023-09-18clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea1-3/+2
2023-09-18clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea1-1/+1
2023-09-11clk: renesas: r9a06g032: Use for_each_compatible_node()Yang Yingliang1-3/+2
2023-08-31Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...Stephen Boyd17-19/+73
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto9-1/+9
2023-07-27clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven1-3/+0
2023-07-25clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das1-0/+3
2023-07-19clk: Explicitly include correct DT includesRob Herring3-4/+1
2023-07-11clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET1-7/+1
2023-07-10clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro1-0/+15
2023-07-10clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford2-4/+32
2023-06-26Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...Stephen Boyd6-49/+27
2023-06-09clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard1-0/+1
2023-06-05clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+5
2023-06-05clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+7
2023-06-05clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-20/+11
2023-05-23clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2-7/+2
2023-05-08clk: renesas: r8a779a0: Add PWM clockWolfram Sang1-0/+1
2023-04-30Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds7-204/+591