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path: root/drivers/clk/renesas
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2019-02-25clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLKFabrizio Castro1-1/+1
2019-02-22clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLKFabrizio Castro1-1/+1
2019-02-05clk: renesas: r8a774c0: Add TMU clockBiju Das1-0/+5
2019-02-05clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov1-0/+8
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2-0/+105
2019-01-25clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov1-0/+8
2019-01-25clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov1-18/+20
2019-01-24clk: renesas: r8a774c0: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2019-01-21clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro1-0/+2
2019-01-21clk: renesas: r8a774c0: Add missing CANFD clockFabrizio Castro1-0/+4
2018-12-15Merge branch 'clk-of' into clk-nextStephen Boyd1-1/+1
2018-12-15clk: Use of_node_name_eq for node name comparisonsRob Herring1-1/+1
2018-12-15Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd9-34/+58
2018-12-11clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd5-8/+8
2018-12-07Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd8-33/+46
2018-12-07clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund1-7/+26
2018-12-07clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund1-5/+5
2018-12-07clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund1-12/+4
2018-12-04clk: renesas: r8a77995: Simplify PLL3 multiplier/dividerGeert Uytterhoeven1-2/+2
2018-12-04clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven1-1/+2
2018-12-04clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven1-1/+0
2018-12-04clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocksGeert Uytterhoeven1-3/+0
2018-12-04clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2018-12-04clk: renesas: r8a77990: Correct parent clock of DUTakeshi Kihara1-2/+2
2018-12-04clk: renesas: r8a77970: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a77965: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a7796: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a7795: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a774a1: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-11-30clk: renesas: Mark rza2_cpg_clk_register staticStephen Boyd1-1/+1
2018-11-13clk: renesas: r7s9210: Add USB clocksChris Brandt1-0/+2
2018-11-05clk: renesas: r8a77970: Add RPC clocksSergei Shtylyov1-0/+4
2018-11-05clk: renesas: r7s9210: Add SDHI clocksChris Brandt1-0/+5
2018-10-19Merge branch 'clk-renesas' into clk-nextStephen Boyd18-168/+1333
2018-10-19Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-nextStephen Boyd10-28/+28
2018-09-29clk: renesas: Convert to SPDX identifiersKuninori Morimoto21-89/+25
2018-09-28clk: renesas: r7s9210: Add SPI clocksChris Brandt1-0/+3
2018-09-26clk: renesas: r7s9210: Move table update to separate functionChris Brandt1-45/+50
2018-09-26clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt1-6/+26
2018-09-26clk: renesas: cpg-mssr: Add early clock supportChris Brandt2-21/+89
2018-09-25clk: renesas: r8a77970: Add TPU clockSergei Shtylyov1-0/+1
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven1-2/+2
2018-09-19clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro5-0/+299
2018-09-19clk: renesas: r8a7743: Add r8a7744 supportBiju Das3-2/+18
2018-09-11clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt5-12/+277
2018-09-11clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov1-0/+5
2018-09-11clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov1-0/+4
2018-09-11clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy1-1/+2
2018-09-03clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2-2/+67
2018-09-03clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov1-0/+4