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path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2022-09-18clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven1-0/+3
2022-09-18clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven1-0/+4
2022-09-18clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven1-0/+6
2022-09-18clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven1-0/+1
2022-08-29clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang1-0/+4
2022-08-29clk: renesas: r9a09g011: Add IIC clock and reset entriesPhil Edworthy1-0/+4
2022-08-22clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_infoBiju Das1-0/+2
2022-08-22clk: renesas: r8a779f0: Add TMU and parent SASYNC clocksWolfram Sang1-0/+10
2022-08-15clk: renesas: r8a779f0: Add CMT clocksWolfram Sang1-0/+4
2022-08-15clk: renesas: r8a779f0: Add SDH0 clockWolfram Sang1-1/+2
2022-07-05clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_configAndi Kleen1-1/+1
2022-07-05clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar1-0/+32
2022-06-17clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang1-0/+4
2022-06-17clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda1-0/+2
2022-06-17clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven1-0/+2
2022-06-13clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven1-18/+15
2022-06-13clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven1-18/+9
2022-06-13clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven1-22/+9
2022-06-13clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven1-13/+13
2022-06-13clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven1-10/+10
2022-06-13clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven1-11/+11
2022-06-13clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang1-0/+1
2022-06-13clk: renesas: r8a779f0: Add thermal clockWolfram Sang1-0/+1
2022-06-07clk: renesas: rzg2l: Fix reset status functionBiju Das1-1/+1
2022-06-06clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen1-4/+4
2022-06-06clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen1-13/+11
2022-06-06clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy1-0/+3
2022-06-06clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy1-0/+2
2022-06-06clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das1-1/+13
2022-06-06clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das1-1/+4
2022-05-29Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds1-1/+39
2022-05-19clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal1-0/+5
2022-05-19clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal1-1/+34
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy1-5/+9
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy5-0/+181
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2-3/+17
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy4-1/+16
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy3-31/+19
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy3-6/+12
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy3-22/+19
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven1-1/+1
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das1-0/+9
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das1-0/+18
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das1-1/+16
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das1-1/+8
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das1-1/+18
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das1-1/+4
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das1-1/+4