summaryrefslogtreecommitdiff
path: root/drivers/clk/spear
AgeCommit message (Expand)AuthorFilesLines
2014-07-13Merge branch 'clk-fixes' into clk-nextMike Turquette1-5/+11
2014-07-13clk: spear3xx: Set proper clock parent of uart1/2Thomas Gleixner1-4/+10
2014-07-13clk: spear3xx: Use proper control register offsetThomas Gleixner1-1/+1
2014-07-11ARM: SPEAr13xx: Fix pcie clock namePratyush Anand2-4/+4
2013-12-19clk: SPEAr: Staticize clk_frac_opsSachin Kamat1-1/+1
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan4-167/+201
2013-06-12clk: spear: fix build error for spear3xxArnd Bergmann1-1/+1
2013-05-02Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds4-106/+112
2013-03-22clk:SPEAr1340: Correct parent clock configurationVipul Kumar Samar1-9/+9
2013-03-12ARM: spear: make clock driver independent of headersArnd Bergmann4-106/+112
2012-12-15Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+1
2012-11-26ARM: SPEAr1310: Move 1310 specific misc register into machine specific filesVipul Kumar Samar1-0/+1
2012-11-21CLK: SPEAr: Remove unused dummy apb_pclkVipul Kumar Samar4-12/+0
2012-11-21CLK: SPEAr: Correct index scanning done for clock synthsDeepak Sikri1-0/+3
2012-11-21CLK: SPEAr: Update clock rate tableDeepak Sikri4-21/+89
2012-11-21CLK: SPEAr: Add missing clocksVipul Kumar Samar3-0/+16
2012-11-21CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocksVipul Kumar Samar5-114/+133
2012-11-21CLK: SPEAr13xx: fix parent names of multiple clocksShiraz Hashim2-4/+4
2012-11-21CLK: SPEAr13xx: Fix mux clock namesShiraz Hashim2-12/+12
2012-11-21CLK: SPEAr: Fix dev_id & con_id for multiple clocksRajeev Kumar4-41/+49
2012-11-15clk: spear: Add stub functions for spear3[0|1|2]0_clk_init()Axel Lin1-0/+6
2012-10-29clk: SPEAr: Vco-pll: Fix compilation warningViresh Kumar1-1/+1
2012-07-18Clk: SPEAr1340: Update sys clock parent arrayVipul Kumar Samar1-2/+2
2012-07-18clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.Vipul Kumar Samar1-2/+2
2012-07-18Clk:spear6xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-62/+60
2012-07-18Clk:spear3xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-94/+86
2012-07-18clk:spear1310:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-157/+155
2012-07-18clk:spear1340:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-138/+135
2012-06-26clk: SPEAr600: Fix ethernet clock name for DT based probingStefan Roese1-1/+1
2012-06-21Viresh has movedViresh Kumar10-10/+10
2012-05-14SPEAr13xx: Add common clock framework supportViresh Kumar3-0/+2072
2012-05-12SPEAr: Switch to common clock frameworkViresh Kumar3-0/+957
2012-05-12SPEAr: clk: Add General Purpose Timer Synthesizer clockViresh Kumar3-1/+172
2012-05-12SPEAr: clk: Add Fractional Synthesizer clockViresh Kumar3-1/+182
2012-05-12SPEAr: clk: Add Auxiliary Synthesizer clockViresh Kumar3-1/+242
2012-05-12SPEAr: clk: Add VCO-PLL Synthesizer clockViresh Kumar4-0/+462