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path: root/drivers/clk/sunxi-ng
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2021-05-24clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audioTobias Schramm1-2/+2
2021-03-06clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pllTobias Schramm1-11/+22
2021-02-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds7-7/+1272
2021-02-12clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec1-1/+1
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 CCUAndre Przywara4-0/+1212
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 R-CCUAndre Przywara2-1/+49
2021-01-20clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara1-4/+4
2021-01-06clk: sunxi-ng: h6: Fix CEC clockAndre Przywara1-1/+1
2021-01-06clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and resetSamuel Holland2-1/+6
2020-12-20clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec2-0/+2
2020-08-25clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLLJernej Skrabec1-13/+24
2020-08-25clk: sunxi-ng: add support for the Allwinner A100 CCUYangtao Li6-0/+1579
2020-02-12clk: sunxi-ng: sun8i-de2: Sort structuresJernej Skrabec1-10/+10
2020-02-12clk: sunxi-ng: sun8i-de2: Add R40 specific quirksJernej Skrabec1-0/+14
2020-02-12clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83TJernej Skrabec1-1/+11
2020-02-12clk: sunxi-ng: sun8i-de2: Don't reuse A83T resetsJernej Skrabec1-7/+16
2020-02-12clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate coreJernej Skrabec1-56/+1
2020-02-12clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64Jernej Skrabec1-3/+42
2020-02-12clk: sunxi-ng: sun8i-de2: Split out H5 definitionsJernej Skrabec1-1/+17
2020-02-11clk: sunxi-ng: a64: Export MBUS clockJernej Skrabec1-4/+0
2020-02-04Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds5-8/+33
2020-01-04clk: sunxi: a23/a33: Export the MIPI PLLMaxime Ripard1-1/+3
2020-01-04clk: sunxi: a31: Export the MIPI PLLMaxime Ripard1-1/+3
2020-01-04clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick1-1/+0
2020-01-04clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng1-1/+27
2020-01-03clk: sunxi-ng: r40: Export MBUS clockChen-Yu Tsai1-4/+0
2020-01-02clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland1-2/+2
2020-01-02clk: sunxi-ng: h6-r: Simplify R_APB1 clock definitionSamuel Holland1-11/+1
2020-01-02clk: sunxi-ng: sun8i-r: Fix divider on APB0 clockSamuel Holland1-18/+3
2019-12-19clk: sunxi-ng: r40: Allow setting parent rate for external clock outputsChen-Yu Tsai1-2/+4
2019-12-09clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.Yunhao Tian2-4/+2
2019-12-02Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-11/+16
2019-11-05clk: sunxi-ng: h3: Export MBUS clockJernej Skrabec1-4/+0
2019-10-29clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18Colin Ian King1-1/+1
2019-10-02clk: sunxi-ng: h6: Allow GPU to change parent rateJernej Skrabec1-1/+1
2019-09-30clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLLJernej Skrabec1-6/+15
2019-09-20Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' i...Stephen Boyd4-14/+255
2019-08-21clk: sunxi-ng: h6: Allow I2S to change parent rateJernej Skrabec1-4/+4
2019-08-16clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registeredStephen Boyd1-2/+3
2019-08-12clk: sunxi-ng: v3s: add Allwinner V3 supportIcenowy Zheng2-3/+227
2019-08-12clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocksIcenowy Zheng1-0/+3
2019-07-22clk: sunxi-ng: v3s: add the missing PLL_DDR1Icenowy Zheng2-6/+19
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds16-221/+397
2019-06-25Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/p...Stephen Boyd16-220/+396
2019-06-22clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-14/+23
2019-06-22clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATEChen-Yu Tsai1-12/+20
2019-06-22clk: sunxi-ng: gate: Add macros for referencing local clock parentsChen-Yu Tsai1-0/+53
2019-06-22clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
2019-06-22clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-25/+44
2019-06-22clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-15/+26