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path: root/drivers/clk/sunxi-ng
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2019-06-18clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-1/+1
2019-06-18clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
2019-06-18clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-17/+29
2019-06-18clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-10/+19
2019-06-18clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
2019-06-18clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
2019-06-18clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-14/+25
2019-06-18clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-12/+22
2019-06-18clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTORChen-Yu Tsai1-14/+25
2019-06-18clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*Chen-Yu Tsai1-40/+25
2019-06-18clk: sunxi-ng: switch to of_clk_hw_register() for registering clksChen-Yu Tsai1-1/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner28-252/+28
2019-06-05clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate registerOndrej Jirman1-1/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner15-150/+15
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner13-65/+13
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd26-0/+26
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd2-3/+3
2019-05-07Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a...Stephen Boyd6-13/+23
2019-05-01clk: sunxi-ng: Use the correct style for SPDX License IdentifierNishad Kamdar2-3/+3
2019-04-10clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard1-4/+0
2019-04-09clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai1-2/+3
2019-04-04clk: sunxi-ng: nkmp: Explain why zero width check is neededJernej Skrabec1-0/+6
2019-04-04clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec1-3/+3
2019-04-03clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec1-0/+11
2019-04-03clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)Jernej Skrabec1-5/+13
2019-03-18clk: sunxi-ng: f1c100s: fix USB PHY gate bit offsetIcenowy Zheng1-1/+1
2019-03-18clk: sunxi-ng: Allow DE clock to set parent rateJernej Skrabec3-3/+5
2019-03-08Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', '...Stephen Boyd1-1/+1
2019-01-28clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara1-2/+2
2019-01-25clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai1-1/+1
2019-01-22clk: sunxi-ng: v3s: Fix TCON reset de-assert bitPaul Kocialkowski1-1/+1
2018-12-10clk: sunxi-ng: a64: Allow parent change for VE clockJernej Skrabec1-1/+1
2018-12-05clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai1-3/+3
2018-12-05clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLLChen-Yu Tsai1-13/+24
2018-12-04clk: sunxi-ng: h3: Allow parent change for ve clockJernej Skrabec1-1/+1
2018-12-04clk: sunxi-ng: add support for suniv F1C100s SoCMesih Kilinc4-0/+581
2018-12-03clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai1-1/+1
2018-11-30clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC outputChen-Yu Tsai1-0/+11
2018-11-23clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLLChen-Yu Tsai1-13/+24
2018-11-13clk: sunxi-ng: a64: Fix gate bit of DSI DPHYJagan Teki1-1/+1
2018-11-13clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50IJagan Teki1-0/+1
2018-11-05clk: sunxi-ng: Add support for H6 DE3 clocksJernej Skrabec2-4/+71
2018-11-05clk: sunxi-ng: h6: Set video PLLs limitsJernej Skrabec1-0/+4
2018-11-05clk: sunxi-ng: Use u64 for calculation of NM rateJernej Skrabec1-3/+15
2018-11-05clk: sunxi-ng: Adjust MP clock parent rate when allowedJernej Skrabec1-2/+62
2018-11-05clk: sunxi-ng: sun50i: h6: Fix MMC clock mux widthJagan Teki1-3/+3
2018-11-05clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clockIcenowy Zheng1-1/+6
2018-10-31Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds10-86/+143
2018-09-07clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest settingChen-Yu Tsai1-1/+9