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path: root/drivers/clk/tegra/clk-tegra-periph.c
AgeCommit message (Expand)AuthorFilesLines
2021-08-11clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko1-5/+1
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko1-3/+3
2020-12-10clk: tegra: Fix duplicated SE clock entryDmitry Osipenko1-1/+1
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren1-1/+5
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding1-8/+0
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2018-12-15clk: tegra: get rid of duplicate definesMarcel Ziswiler1-3/+0
2018-07-26clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver1-11/+0
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko1-0/+1
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding1-16/+0
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding1-4/+1
2017-08-24clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid1-1/+2
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver1-0/+6
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver1-0/+21
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Correct afi clock parentPeter De Schrijver1-1/+1
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver1-2/+9
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding1-1/+1
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding1-11/+12
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding1-2/+0
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding1-0/+1
2016-04-28clk: tegra: Use correct parent for dpaux clockThierry Reding1-1/+1
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding1-1/+1
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding1-1/+1
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter1-0/+1
2016-02-02clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein1-1/+1
2016-01-25clk: tegra: Fix divider on VI_I2CRhyland Klein1-1/+1
2015-11-20clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein1-4/+367
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
2015-04-10clk: tegra: Fix a bunch of sparse warningsThierry Reding1-1/+1
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-2/+0
2015-02-02clk: tegra: SDMMC controllers are on APBAndrew Bresticker1-8/+8
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver1-2/+2
2014-05-23clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker1-0/+6
2014-05-23clk: tegra: Fix xusb_fs_src muxJim Lin1-1/+3
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver1-3/+1
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker1-0/+4
2014-02-17clk: tegra: Correct clock number for UARTEThierry Reding1-1/+1
2013-11-26clk: tegra124: Add new peripheral clocksPeter De Schrijver1-0/+69
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver1-0/+6
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver1-15/+18
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-0/+596