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path: root/drivers/clk/tegra/clk-tegra114.c
AgeCommit message (Expand)AuthorFilesLines
2018-12-15clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter1-1/+8
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+1
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko1-0/+1
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-2/+1
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding1-3/+1
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2016-08-24clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu1-2/+2
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-154/+2
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding1-1/+5
2016-03-03clk: tegra: Remove CLK_IS_ROOTStephen Boyd1-2/+1
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang1-1/+2
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-51/+71
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-10/+13
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-4/+4
2015-11-18clk: tegra: Format tables consistentlyThierry Reding1-136/+137
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-6/+6
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding1-1/+1
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein1-1/+7
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-2/+0
2015-04-10clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding1-31/+3
2015-04-10clk: tegra: Various whitespace cleanupsThierry Reding1-1/+1
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-2/+8
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+6
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver1-1/+30
2014-05-23clk: tegra: Initialize xusb clocksAndrew Bresticker1-1/+6
2014-05-23clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker1-10/+5
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker1-4/+4
2013-12-12clk: tegra: implement a reset driverStephen Warren1-1/+2
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding1-0/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot1-0/+1
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen1-0/+2
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver1-74/+2
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver1-74/+1
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-574/+17
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver1-208/+182
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver1-159/+163
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver1-31/+43
2013-11-26clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver1-1/+2
2013-11-26clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver1-89/+20
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver1-41/+16
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver1-235/+141
2013-11-26clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding1-4/+4
2013-11-26clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew1-0/+1
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver1-24/+29
2013-11-25clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang1-0/+3
2013-11-25clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang1-10/+3
2013-11-25clk: tegra: Correct sbc mux width & parentMark Zhang1-6/+6
2013-11-25clk: tegra: replace enum tegra114_clk by binding headerPeter De Schrijver1-233/+198
2013-09-10Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds1-13/+25
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-12/+24