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path: root/drivers/clk/tegra/clk-tegra210.c
AgeCommit message (Expand)AuthorFilesLines
2017-08-24clk: tegra: Fix Tegra210 PLLU initializationAlex Frid1-2/+4
2017-08-24clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid1-3/+3
2017-08-24clk: tegra: Re-factor T210 PLLX registrationAlex Frid1-1/+1
2017-08-24clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver1-2/+4
2017-08-24clk: tegra: Fix T210 effective NDIV calculationAlex Frid1-4/+5
2017-08-24clk: tegra210: remove non-existing VFIR clockPeter De Schrijver1-1/+0
2017-08-24clk: tegra: disable SSC for PLL_D2Peter De Schrijver1-1/+1
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter1-4/+4
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver1-0/+7
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver1-0/+2
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver1-0/+25
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver1-0/+85
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver1-23/+272
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver1-0/+26
2017-03-20clk: tegra: Add aclkPeter De Schrijver1-0/+10
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver1-0/+3
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver1-0/+6
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver1-1/+7
2017-03-20clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver1-6/+12
2017-03-20clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver1-5/+0
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver1-1/+2
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-179/+3
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding1-4/+4
2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding1-2/+2
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding1-0/+2
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding1-2/+3
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding1-47/+47
2016-05-28remove lots of IS_ERR_VALUE abusesArnd Bergmann1-1/+1
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein1-2/+14
2016-04-28clk: tegra: Add sor_safe clockThierry Reding1-0/+4
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding1-0/+8
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding1-0/+1
2016-04-28clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker1-0/+58
2016-02-02clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter1-17/+19
2016-02-02clk: tegra: Fix sparse warning for pll_mJon Hunter1-1/+1
2016-02-02clk: tegra: Use definition for pll_u override bitJon Hunter1-1/+1
2016-02-02clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter1-2/+0
2016-02-02clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter1-1/+2
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter1-0/+1
2016-02-02clk: tegra: Fix pllx dyn step calculationRhyland Klein1-5/+5
2016-02-02clk: tegra: Fix naming of MISC registersRhyland Klein1-18/+18
2016-01-25clk: tegra: Remove improper flags for lock_enableRhyland Klein1-28/+14
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein1-0/+2852