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path: root/drivers/clk/tegra/clk.h
AgeCommit message (Expand)AuthorFilesLines
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2018-12-15clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter1-2/+2
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver1-0/+26
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver1-0/+3
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo1-0/+1
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+1
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver1-0/+7
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding1-0/+3
2017-08-24clk: tegra: Re-factor T210 PLLX registrationAlex Frid1-6/+0
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding1-1/+1
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver1-1/+6
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver1-2/+2
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver1-1/+1
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-0/+17
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein1-0/+6
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding1-0/+17
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding1-2/+2
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein1-0/+3
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang1-0/+3
2015-12-17clk: tegra: pll: Add logic for SSBill Huang1-0/+4
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein1-0/+4
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang1-0/+11
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang1-0/+4
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein1-0/+9
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein1-0/+24
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang1-0/+4
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein1-0/+13
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein1-1/+14
2015-11-20clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang1-1/+3
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein1-0/+1
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-1/+1
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein1-1/+17
2015-10-20clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding1-3/+15
2015-10-20clk: tegra: Fix comments for structure definitionsRhyland Klein1-37/+37
2015-07-16clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen1-0/+3
2015-05-13clk: tegra: EMC clock driver depends on EMC driverThierry Reding1-0/+9
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen1-0/+3
2015-04-10clk: tegra: Model oscillator as clockThierry Reding1-4/+4
2015-04-10clk: tegra: Fix typo tabel -> tableThierry Reding1-1/+1
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-0/+2
2013-12-12clk: tegra: remove legacy reset APIsStephen Warren1-1/+0
2013-12-12clk: tegra: implement a reset driverStephen Warren1-1/+1
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver1-0/+1
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver1-4/+6
2013-11-26clk: tegra: Add support for PLLSSPeter De Schrijver1-0/+5
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver1-0/+3
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver1-0/+7
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-2/+9
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver1-0/+4
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver1-0/+7