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path: root/drivers/clk/tegra
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2018-12-15Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd10-32/+80
2018-12-15clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang1-3/+4
2018-12-15clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter1-3/+3
2018-12-15clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter7-13/+37
2018-12-15clk: tegra: get rid of duplicate definesMarcel Ziswiler1-3/+0
2018-11-29clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li1-11/+1
2018-11-08clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko1-0/+10
2018-11-08clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko1-10/+26
2018-10-17clk: tegra210: Include size.h for compilation easeStephen Boyd1-0/+1
2018-10-17clk: tegra: Fixes for MBIST work aroundJoseph Lo1-3/+3
2018-10-17clk: tegra: probe deferral error reportingMarcel Ziswiler1-2/+6
2018-08-15Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd8-40/+343
2018-08-15Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd4-7/+15
2018-07-26clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver3-15/+12
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver3-0/+278
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver4-25/+52
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo1-0/+1
2018-07-09clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
2018-07-09clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
2018-07-09clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
2018-07-09clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
2018-07-09clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
2018-06-13treewide: kzalloc() -> kcalloc()Kees Cook1-3/+4
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Stephen Boyd1-31/+11
2018-06-02clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman1-31/+11
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko7-8/+39
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko1-4/+2
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko1-0/+14
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler1-0/+2
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko4-1/+4
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko1-3/+3
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko8-36/+26
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver1-2/+342
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver1-0/+7
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver1-0/+14
2017-11-18Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds13-66/+102
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2-0/+2
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen3-13/+11
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko1-5/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko4-0/+4
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter1-1/+1
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal1-8/+8
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding2-16/+47
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding4-13/+4
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding2-0/+11
2017-10-19clk: tegra: Check BPMP response return codeTimo Alho1-5/+10