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path: root/drivers/clk/zynq
AgeCommit message (Expand)AuthorFilesLines
2018-08-30clk: Convert to using %pOFn instead of device_node.nameRob Herring1-2/+2
2016-03-03clk: zynq: Remove CLK_IS_ROOTStephen Boyd1-2/+1
2015-09-01Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/a...Linus Torvalds1-1/+1
2015-07-31clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in MakefileMasahiro Yamada1-1/+1
2015-07-20clk: zynq: Include clk.hStephen Boyd1-0/+1
2015-06-05clk: make several parent names constUwe Kleine-König1-9/+16
2015-04-13clk: don't use __initconst for non-const arraysUwe Kleine-König1-12/+12
2015-01-28clk: zynq: Force CPU_2X clock to be ungatedSoren Brinkmann1-0/+1
2014-09-09clk: zynq: Move const initdata into correct code sectionSoren Brinkmann1-15/+14
2014-09-09clk: zynq: Remove pointless return at end of void functionSoren Brinkmann1-1/+0
2014-09-09clk: zynq: Remove unnecessary OOM messageSoren Brinkmann1-3/+1
2014-04-22clk: zynq: Leave debug clocks in bootup stateSoren Brinkmann1-0/+12
2014-04-06Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds2-11/+11
2014-03-17ARM: zynq: Move of_clk_init from clock driverMichal Simek1-2/+0
2014-02-26clk: zynq: Use clk_readl/clk_writel helper functionMichal Simek2-11/+11
2014-02-10ARM: zynq: Map I/O memory on clkc initMichal Simek1-26/+63
2013-12-20clk/zynq/clkc: Add 'fclk-enable' featureSoren Brinkmann1-3/+15
2013-10-08clk/zynq: Fix possible memory leakFelipe Pena1-1/+15
2013-09-10Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2-39/+62
2013-08-21Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-nextMike Turquette1-5/+14
2013-08-20clk/zynq/pll: Use #defines for fbdiv min/max valuesSoren Brinkmann1-4/+7
2013-08-20clk/zynq/pll: Fix documentation for PLL register functionSoren Brinkmann1-1/+7
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-36/+50
2013-08-13clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxesSoren Brinkmann1-4/+6
2013-08-13clk/zynq/clkc: Add dedicated spinlock for the SWDTSoren Brinkmann1-1/+2
2013-05-27arm: zynq: Migrate platform to clock controllerSoren Brinkmann1-0/+3
2013-05-27clk: zynq: Add clock controller driverSoren Brinkmann1-0/+533
2013-05-21clk: zynq: Factor out PLL driverSoren Brinkmann1-0/+235