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2023-04-14clk: starfive: Avoid casting iomem pointersStephen Boyd1-3/+12
Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip up tools like sparse, and make for some awkward casts that are largely unnecessary. While we're here, change the allocation from devm and actually free the auxiliary_device memory in the release function. This avoids any use after free problems where the parent device driver is unbound from the device but the auxiliuary_device is still in use accessing devm freed memory. Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: Hal Feng <hal.feng@starfivetech.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230413205528.4044216-1-sboyd@kernel.org
2023-04-05clk: starfive: Add StarFive JH7110 always-on clock driverEmil Renner Berthing3-0/+168
Add driver for the StarFive JH7110 always-on clock controller and register an auxiliary device for always-on reset controller which is named as "rst-aon". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Add StarFive JH7110 system clock driverEmil Renner Berthing4-0/+514
Add driver for the StarFive JH7110 system clock controller and register an auxiliary device for system reset controller which is named as "rst-sys". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Rename "jh7100" to "jh71x0" for the common codeEmil Renner Berthing4-406/+418
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.hEmil Renner Berthing4-3/+3
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making the code to be common. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Factor out common JH7100 and JH7110 codeEmil Renner Berthing5-326/+342
The clock control registers on the StarFive JH7100 and JH7110 work identically, so factor out the code then drivers for the two SoCs can share it without depending on each other. No functional change. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng2-4/+4
Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-02-26Merge tag 'clk-for-linus' of ↵Linus Torvalds201-6092/+18873
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have one small patch to the clk core this time around. It fixes a corner case with the CLK_OPS_PARENT_ENABLE flag combined with clk_core_is_enabled() where it hangs the system. We'll simply assume the clk is disabled if the parent is disabled and the flag is set. Trying to turn on the parent to check the enable state of the clk runs into system hangs at boot. We let this bake in -next for a couple weeks to make sure there aren't any more issues because the last attempt to fix this ran into hangs and had to be reverted. Note: There were some more patches to the core framework around sync_state and disabling unused clks, but I asked for that to be reverted from the qcom PR because it isn't ready and we're still discussing the best solution on the list. Outside of the core clk framework, we have the usual collection of clk driver updates and support for new SoCs (which seems to never stop). The dirstat is dominated by Qualcomm because they added support for quite a few SoCs this time around and also migrated quite a few of their drivers to clk_parent_data. The other big diff is in the Mediatek clk drivers that saw a significant rework this cycle to similarly modernize the code, and we'll see that work continue in the next cycle as well. Nothing really jumps out as scary here, except that the significant churn in parent data descriptions can have typos that go unnoticed. More details below. Core: - Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() New Drivers: - Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref clocks - Support for Mediatek MT7891 SoC clks - Support for many Qualcomm clk controllers: - QDU1000/QRU1000 global clock controller - SA8775P global clock controller - SM8550 TCSR and display clock controller - SM6350 clock controller - MSM8996 CBF and APCS clock controllers Updates: - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Versa 5P49V60 clks - Disable R-Car H3 ES1.*, as it was only available to an internal development group and needed a lot of quirks and workarounds - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and resets on Renesas RZ/V2M - Add display clocks on Renesas R-Car V4H - Add Camera Receiving Unit (CRU) clocks and resets on Renesas RZ/G2L - Free the imx_uart_clocks even if imx_register_uart_clocks returns early - Get the stdout clocks count from device tree on i.MX - Drop the clock count argument from imx_register_uart_clocks() - Keep the uart clocks on i.MX93 for when earlycon is used - Fix SPDX comment in i.MX6SLL clocks bindings header - Drop some unnecessary spaces from i.MX8ULP clocks bindings header - Add imx_obtain_fixed_of_clock() for allowing to add a clock that is not configured via devicetree - Fix the ENET1 gate configuration for i.MX6UL according to the reference manual - Add ENET refclock mux support for i.MX6UL - Add support for USB host/device configuration on Renesas RZ/N1 - Add PLL2 programming support, and CAN-FD clocks on Renesas R-Car V4H - Add D1 CAN bus gates and resets for Allwinner - Mark D1 CPUX clock as critical on Allwinner - Reuse D1 driver for Allwinner R528/T113 - Cleanup sunxi-ng Kconfig - Fix sunxi-ng kernel-doc issues - Model Allwinner H3/H5 DRAM clock as fixed clock - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll, sclk-div and cpu-dyn-div amlogic clock drivers - DDR clocks were marked as critical in the proper clock driver for each AT91 SoC such that drivers/memory/atmel-sdramc.c to be deleted in the next releases as it only does clock enablement - Patch to avoid compiling dt-compat.o for all AT91 SoCs as only some of them may use it - Support synchronous power_off requests in the qcom GDSC driver for proper GPU power collapse - Drop test clocks from various Qualcomm clk drivers - Update parent references to use clk_parent_data/clk_hw in various Qualcomm clk drivers - Fixes for the Qualcomm MSM8996 CPU clock controller - Transition Qualcomm MSM8974 GCC off the externally defined sleep_clk - Add GDSCs in the global clock controller for Qualcomm QCS404 - The SDCC core clocks on Qualcomm SM6115 are moved to floor_ops - Programming of clk_dis_wait for GPU CX GDSC on Qualcomm SC7180 and SDM845 are moved to use the recently introduced properties in the GDSC struct - Qualcomm's RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock is added on a variety of platforms - De-duplicate identical clks in Qualcomm SMD RPM clk driver - Add a few missing clocks across msm8998, msm8992, msm8916, qcs404 to Qualcomm SDM RPM clk driver - Various Qualcomm clk drivers use devm_pm_runtime_enable() to simplify" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (228 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused clk: imx: pll14xx: fix recalc_rate for negative kdiv clk: rs9: Drop unused pin_xin field MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function clk: mediatek: clk-mtk: Remove unneeded semicolon dt-bindings: clock: remove stih416 bindings dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file clk: imx: fix compile testing imxrt1050 clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include ...
2023-02-24Merge tag 'usb-6.3-rc1' of ↵Linus Torvalds1-0/+28
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt driver updates from Greg KH: "Here is the big set of USB and Thunderbolt driver changes for 6.3-rc1. Nothing major in here, just lots of good development, including: - Thunderbolt additions for new device support and features - xhci driver updates and cleanups - USB gadget media driver updates (includes media core changes that were acked by the v4l2 maintainers) - lots of other USB gadget driver updates for new features - dwc3 driver updates and fixes - minor debugfs leak fixes - typec driver updates and additions - dt-bindings conversions to yaml - other small bugfixes and driver updates All have been in linux-next for a while with no reported issues" * tag 'usb-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (237 commits) usb: dwc3: xilinx: Remove unused of_gpio,h usb: typec: pd: Add higher capability sysfs for sink PDO usb: typec: pd: Remove usb_suspend_supported sysfs from sink PDO usb: dwc3: pci: add support for the Intel Meteor Lake-M usb: gadget: u_ether: Don't warn in gether_setup_name_default() usb: gadget: u_ether: Convert prints to device prints usb: gadget: u_serial: Add null pointer check in gserial_resume usb: gadget: uvc: fix missing mutex_unlock() if kstrtou8() fails xhci: host: potential NULL dereference in xhci_generic_plat_probe() dt-bindings: usb: amlogic,meson-g12a-usb-ctrl: make G12A usb3-phy0 optional usb: host: fsl-mph-dr-of: reuse device_set_of_node_from_dev of: device: Do not ignore error code in of_device_uevent_modalias of: device: Ignore modalias of reused nodes usb: gadget: configfs: Fix set but not used variable warning usb: gadget: uvc: Use custom strings if available usb: gadget: uvc: Allow linking function to string descs usb: gadget: uvc: Pick up custom string descriptor IDs usb: gadget: uvc: Allow linking XUs to string descriptors usb: gadget: configfs: Attach arbitrary strings to cdev usb: gadget: configfs: Support arbitrary string descriptors ...
2023-02-23Merge branches 'clk-loongson' and 'clk-qcom' into clk-nextStephen Boyd52-3504/+15041
* clk-loongson: dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file * clk-qcom: (143 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include clk: qcom: gcc-sa8775p: remove unused variables clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform clk: qcom: add msm8996 Core Bus Framework (CBF) support dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller clk: qcom: add the driver for the MSM8996 APCS clocks clk: qcom: gcc-qcs404: fix duplicate initializer warning clk: qcom: cpu-8996: change setup sequence to follow vendor kernel clk: qcom: cpu-8996: fix PLL clock ops clk: qcom: cpu-8996: fix ACD initialization clk: qcom: cpu-8996: fix PLL configuration sequence clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call clk: qcom: cpu-8996: setup PLLs before registering clocks clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb ...
2023-02-23Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' ↵Stephen Boyd129-2359/+3465
and 'clk-core' into clk-next - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Mediatek MT7891 SoC clks * clk-microchip: clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60 clk: at91: mark ddr clocks as critical * clk-allwinner: clk: sunxi-ng: d1: Add CAN bus gates and resets dt-bindings: clock: Add D1 CAN bus gates and resets clk: sunxi-ng: d1: Mark cpux clock as critical clk: sunxi-ng: d1: Allow building for R528/T113 clk: sunxi-ng: Move SoC driver conditions to dependencies clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies clk: sunxi-ng: Avoid computing the rate twice clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues * clk-mediatek: (29 commits) clk: mediatek: clk-mtk: Remove unneeded semicolon clk: mediatek: remove MT8195 vppsys/0/1 simple_probe dt-bindings: arm: mediatek: migrate MT8195 vppsys0/1 to mtk-mmsys driver clk: mediatek: add MT7981 clock support dt-bindings: clock: mediatek: add mt7981 clock IDs dt-bindings: clock: Add compatibles for MT7981 clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs clk: mediatek: mt8186: Join top_adj_div and top_muxes clk: mediatek: mt8192: Join top_adj_divs and top_muxes clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() clk: mediatek: Switch to mtk_clk_simple_probe() where possible clk: mediatek: mt8173: Break down clock drivers and allow module build ... * clk-imx: clk: imx: pll14xx: fix recalc_rate for negative kdiv MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: imx: fix compile testing imxrt1050 clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: imx6ul: add ethernet refclock mux support clk: imx6ul: fix enet1 gate configuration clk: imx: add imx_obtain_fixed_of_clock() clk: imx6q: add ethernet refclock mux support clk: imx: add clk-gpr-mux driver dt-bindings: imx8ulp: clock: no spaces before tabs clk: imx6sll: add proper spdx license identifier clk: imx: imx93: invoke imx_register_uart_clocks clk: imx: remove clk_count of imx_register_uart_clocks clk: imx: get stdout clk count from device tree clk: imx: avoid memory leak * clk-core: clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()
2023-02-23Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and ↵Stephen Boyd17-225/+385
'clk-amlogic' into clk-next - Support for Versa 5P49V60 clks * clk-cleanup: clk: rs9: Drop unused pin_xin field clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function dt-bindings: clock: remove stih416 bindings drivers/clk: Remove "select SRCU" * clk-bindings: dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name * clk-renesas: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* clk: renesas: r8a779g0: Add CAN-FD clocks clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779g0: Add custom clock for PLL2 clk: renesas: cpg-mssr: Remove superfluous check in resume code clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries * clk-versa: dt-bindings: clock: versaclock5: Document 5P49V60 compatible string clk: vc5: Add support for 5P49V60 clk: vc5: Use `clamp()` to restrict PLL range * clk-amlogic: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: mpll: Switch from .round_rate to .determine_rate
2023-02-23clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREPStephen Boyd1-0/+1
Otherwise some configurations fail. Fixes: 027726365906 ("clk: qcom: add the driver for the MSM8996 APCS clocks") Link: https://lore.kernel.org/r/20230223013847.1218900-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-22clk: qcom: Revert sync_state based clk_disable_unusedBjorn Andersson7-52/+11
Revert the postponement of clk_disable_unused() for clock providers that implement sync_state, and the change to drivers implementing this, until agreement on the implementation has been reached. This reverts: 29e31415e14e ("clk: qcom: Remove need for clk_ignore_unused on sc8280xp") 99c0f7d35c4b ("clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callback") 26b36df75166 ("clk: Add generic sync_state callback for disabling unused clocks") Requested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-02-21clk: imx: pll14xx: fix recalc_rate for negative kdivKevin Groeneveld1-1/+1
kdiv is a signed 16 bit value in the DEV_CTL1 register. Commit 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") changed the kdiv variable from a short int to just int. When the value read from the DIV_CTL1 register is assigned directly to an int the sign of the value is lost resulting in incorrect results when the value is negative. Adding a s16 cast to the register value fixes the issue. Fixes: 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com> Link: https://lore.kernel.org/r/20221210203835.9714-1-kgroeneveld@lenbrook.com Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-21Merge tag 'sched-core-2023-02-20' of ↵Linus Torvalds1-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler updates from Ingo Molnar: - Improve the scalability of the CFS bandwidth unthrottling logic with large number of CPUs. - Fix & rework various cpuidle routines, simplify interaction with the generic scheduler code. Add __cpuidle methods as noinstr to objtool's noinstr detection and fix boatloads of cpuidle bugs & quirks. - Add new ABI: introduce MEMBARRIER_CMD_GET_REGISTRATIONS, to query previously issued registrations. - Limit scheduler slice duration to the sysctl_sched_latency period, to improve scheduling granularity with a large number of SCHED_IDLE tasks. - Debuggability enhancement on sys_exit(): warn about disabled IRQs, but also enable them to prevent a cascade of followup problems and repeat warnings. - Fix the rescheduling logic in prio_changed_dl(). - Micro-optimize cpufreq and sched-util methods. - Micro-optimize ttwu_runnable() - Micro-optimize the idle-scanning in update_numa_stats(), select_idle_capacity() and steal_cookie_task(). - Update the RSEQ code & self-tests - Constify various scheduler methods - Remove unused methods - Refine __init tags - Documentation updates - Misc other cleanups, fixes * tag 'sched-core-2023-02-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (110 commits) sched/rt: pick_next_rt_entity(): check list_entry sched/deadline: Add more reschedule cases to prio_changed_dl() sched/fair: sanitize vruntime of entity being placed sched/fair: Remove capacity inversion detection sched/fair: unlink misfit task from cpu overutilized objtool: mem*() are not uaccess safe cpuidle: Fix poll_idle() noinstr annotation sched/clock: Make local_clock() noinstr sched/clock/x86: Mark sched_clock() noinstr x86/pvclock: Improve atomic update of last_value in pvclock_clocksource_read() x86/atomics: Always inline arch_atomic64*() cpuidle: tracing, preempt: Squash _rcuidle tracing cpuidle: tracing: Warn about !rcu_is_watching() cpuidle: lib/bug: Disable rcu_is_watching() during WARN/BUG cpuidle: drivers: firmware: psci: Dont instrument suspend code KVM: selftests: Fix build of rseq test exit: Detect and fix irq disabled state in oops cpuidle, arm64: Fix the ARM64 cpuidle logic cpuidle: mvebu: Fix duplicate flags assignment sched/fair: Limit sched slice duration ...
2023-02-21Merge tag 'arm-boardfile-remove-6.3' of ↵Linus Torvalds17-2269/+0
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC boardfile updates from Arnd Bergmann "Unused boardfile removal for 6.3 This is a follow-up to the deprecation of most of the old-style board files that was merged in linux-6.0, removing them for good. This branch is almost exclusively dead code removal based on those annotations. Some device driver removals went through separate subsystem trees, but the majority is in the same branch, in order to better handle dependencies between the patches and avoid breaking bisection. Unfortunately that leads to merge conflicts against other changes in the subsystem trees, but they should all be trivial to resolve by removing the files. See commit 7d0d3fa7339e ("Merge tag 'arm-boardfiles-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") for the description of which machines were marked unused and are now removed. The only removals that got postponed are Terastation WXL (mv78xx0) and Jornada720 (StrongARM1100), which turned out to still have potential users" * tag 'arm-boardfile-remove-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (91 commits) mmc: omap: drop TPS65010 dependency ARM: pxa: restore mfp-pxa320.h usb: ohci-omap: avoid unused-variable warning ARM: debug: remove references in DEBUG_UART_8250_SHIFT to removed configs ARM: s3c: remove obsolete s3c-cpu-freq header MAINTAINERS: adjust SAMSUNG SOC CLOCK DRIVERS after s3c24xx support removal MAINTAINERS: update file entries after arm multi-platform rework and mach-pxa removal ARM: remove CONFIG_UNUSED_BOARD_FILES mfd: remove htc-pasic3 driver w1: remove ds1wm driver usb: remove ohci-tmio driver fbdev: remove w100fb driver fbdev: remove tmiofb driver mmc: remove tmio_mmc driver mfd: remove ucb1400 support mfd: remove toshiba tmio drivers rtc: remove v3020 driver power: remove pda_power supply driver ASoC: pxa: remove unused board support pcmcia: remove unused pxa/sa1100 drivers ...
2023-02-18clk: rs9: Drop unused pin_xin fieldMarek Vasut1-1/+0
The pin_xin field in struct rs9_driver_data is unused, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20221216210922.592926-1-marex@denx.de Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-14Merge 6.2-rc8 into usb-nextGreg Kroah-Hartman2-16/+12
We need the USB fixes in here for testing. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-02-11clk: sprd: Add dependency for SPRD_UMS512_CLKCixi Geng1-0/+2
Add depends on and default for ums512 clk config. Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com> Link: https://lore.kernel.org/r/20230201091300.3201-1-cixi.geng@linux.dev Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-11clk: ralink: fix 'mt7621_gate_is_enabled()' functionSergio Paracuellos1-2/+8
Compiling clock driver with CONFIG_UBSAN enabled shows the following trace: UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15 shift exponent 131072 is too large for 32-bit type 'long unsigned int' CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0 Stack : ... Call Trace: [<80009a58>] show_stack+0x38/0x118 [<8045ce04>] dump_stack_lvl+0x60/0x80 [<80458868>] ubsan_epilogue+0x10/0x54 [<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190 [<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0 [<804bb774>] clk_core_is_enabled+0x34/0x90 [<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 [<80aad900>] clk_disable_unused+0x78/0x120 [<80002030>] do_one_initcall+0x54/0x1f0 [<80a922a4>] kernel_init_freeable+0x280/0x31c [<808047c4>] kernel_init+0x20/0x118 [<80003e58>] ret_from_kernel_thread+0x14/0x1c Shifting a value (131032) larger than the type (32 bit unsigned integer) is undefined behaviour in C. The problem is in 'mt7621_gate_is_enabled()' function which is using the 'BIT()' kernel macro with the bit index for the clock gate to check if the bit is set. When the clock gates structure is created driver is already setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra 'BIT()' mask here. Removing it solve the problem and makes this function correct. However when clock gating is correctly working, the kernel starts disabling those clocks that are not requested. Some drivers for this SoC are older than this clock driver itself. So to avoid the kernel to disable clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL' flag on gates initialization code. Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-11clk: mediatek: clk-mtk: Remove unneeded semicolonYang Li1-1/+1
./drivers/clk/mediatek/clk-mtk.c:518:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3926 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230202010750.79515-1-yang.lee@linux.alibaba.com Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-11clk: imx: fix compile testing imxrt1050Arnd Bergmann4-1/+9
Randconfig testing revealed multiple issues with this driver: ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/imx/clk-imxrt1050.o ERROR: modpost: "imx_clk_hw_pllv3" [drivers/clk/imx/clk-imxrt1050.ko] undefined! ERROR: modpost: "imx_clk_hw_pfd" [drivers/clk/imx/clk-imxrt1050.ko] undefined! Export the necessary symbols from the core clk driver and add the license and author tags. To find this type of problem more easily in the future, also enable building on other platforms, as we do for the other i.MX clk drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20221215165836.2136448-1-arnd@kernel.org Acked-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-11clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()Chen-Yu Tsai1-0/+11
In the previous commits that added CLK_OPS_PARENT_ENABLE, support for this flag was only added to rate change operations (rate setting and reparent) and disabling unused subtree. It was not added to the clock gate related operations. Any hardware driver that needs it for these operations will either see bogus results, or worse, hang. This has been seen on MT8192 and MT8195, where the imp_ii2_* clk drivers set this, but dumping debugfs clk_summary would cause it to hang. Prepare parent on prepare and enable parent on enable dependencies are already handled automatically by the core as part of its sequencing. Whether the case for "enable parent on prepare" should be supported by this flag or not is not clear, and thus ignored for now. This change solely fixes the handling of clk_core_is_enabled, i.e. enabling the parent clock when reading the hardware state. Unfortunately clk_core_is_enabled is called in a variety of places, sometimes with the enable clock already held. To avoid deadlocking, the core will ignore readouts and just return false if CLK_OPS_PARENT_ENABLE is set but the parent isn't currently enabled. Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)") Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230103092330.494102-1-wenst@chromium.org Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-11clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to staticTom Rix1-1/+1
smatch reports drivers/clk/imx/clk-gpr-mux.c:73:22: warning: symbol 'imx_clk_gpr_mux_ops' was not declared. Should it be static? imx_clk_gpr_mux_ops is only used in clk-gpr-mux.c, so it should be static. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230205030138.1723614-1-trix@redhat.com Fixes: ee394f636ad3 ("clk: imx: add clk-gpr-mux driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-02-10clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang5-173/+13
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-02-09clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov1-6/+1
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org
2023-02-09clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov1-6/+1
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-1-dmitry.baryshkov@linaro.org
2023-02-09clk: qcom: cpu-8996: add missing cputype includeKrzysztof Kozlowski1-0/+2
Include asm/cputype.h to fix ARMv7 compile test error: drivers/clk/qcom/clk-cpu-8996.c: In function ‘qcom_cpu_clk_msm8996_acd_init’: drivers/clk/qcom/clk-cpu-8996.c:468:16: error: implicit declaration of function ‘read_cpuid_mpidr’ [-Werror=implicit-function-declaration] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved asm-include after linux/, per Stephen's request] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123201812.1230039-1-krzysztof.kozlowski@linaro.org
2023-02-09clk: qcom: gcc-sa8775p: remove unused variablesBartosz Golaszewski1-20/+0
There are four struct definitions in the driver that aren't used so remove them. Reported-by: kernel test robot <lkp@intel.com> Fixes: ed432b1ed00a ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123103338.230320-1-brgl@bgdev.pl
2023-02-09clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platformDmitry Baryshkov1-0/+2
Extend the list of RPM clocks provided on MSM8996 platform to also include RPM_SMD_XO_CLK_SRC and RPM_SMD_XO_A_CLK_SRC. Fixes: 7066fdd0d742 ("clk: qcom: clk-smd-rpm: add msm8996 rpmclks") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-6-dmitry.baryshkov@linaro.org
2023-02-09clk: qcom: add msm8996 Core Bus Framework (CBF) supportDmitry Baryshkov2-1/+316
Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly based on AngeloGioacchino del Regno's work at [1]. The CBF is an interconnect between two CPU clusters, setting it up properly is required for booting the MSM8996 with all four cores enabled. [1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Dropped partially uninitialized variable "ret" from cbf_clk_notifier_cb()] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-4-dmitry.baryshkov@linaro.org
2023-02-09clk: qcom: add the driver for the MSM8996 APCS clocksDmitry Baryshkov2-1/+89
Add a simple driver handling the APCS clocks on MSM8996. For now it supports just a single aux clock, linking GPLL0 to CPU and CBF clocks. Note, there is little sense in registering sys_apcs_aux as a child of gpll0. The PLL is always-on. And listing the gpll0 as a property of the apcs would delay its probing until the GCC has been probed (while we would like for the apcs to be probed as early as possible). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Fixed spelling of register, per Stephen's feedback] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230126230319.3977109-8-dmitry.baryshkov@linaro.org
2023-02-01clk: mediatek: remove MT8195 vppsys/0/1 simple_probeMoudy Ho2-30/+86
MT8195 VPPSYS0/1 will be probed by the compatible name in the mtk-mmsys driver and then probe its own clock driver as a platform driver. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Link: https://lore.kernel.org/r/20230118031509.29834-4-moudy.ho@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: imx6ul: add ethernet refclock mux supportOleksij Rempel1-0/+26
Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards. clock tree before this patch: fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ after this patch: fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... `--<> enet1_ref_pad |- pll6_enet fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... `--<> enet2_ref_pad Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de
2023-01-31clk: imx6ul: fix enet1 gate configurationOleksij Rempel1-3/+4
According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de
2023-01-31clk: imx: add imx_obtain_fixed_of_clock()Oleksij Rempel2-0/+17
Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-15-o.rempel@pengutronix.de
2023-01-31clk: imx6q: add ethernet refclock mux supportOleksij Rempel1-0/+13
Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards since machine code currently overwrites this default. The machine code will be fixed in a separate patch. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-3-o.rempel@pengutronix.de
2023-01-31clk: imx: add clk-gpr-mux driverOleksij Rempel3-0/+125
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards. Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de
2023-01-31clk: mediatek: add MT7981 clock supportDaniel Golle6-0/+870
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and ethernet subsystem clocks. The drivers are based on clk-mt7981.c which can be found in MediaTek's SDK sources. To be fit for upstream inclusion the driver has been split into clock domains and the infracfg part has been significantly de-bloated by removing all the 1:1 factors (aliases). Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> [sboyd@kernel.org: Add module license] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe()AngeloGioacchino Del Regno1-42/+13
There are no more non-common calls in clk_mt7986_topckgen_probe(): migrate this driver to mtk_clk_simple_probe(). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabledAngeloGioacchino Del Regno1-22/+24
Instead of calling clk_prepare_enable() on a bunch of clocks at probe time, set the CLK_IS_CRITICAL flag to the same as these are required to be always on, and this is the right way of achieving that. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe()AngeloGioacchino Del Regno1-72/+14
Migrate away from custom probe functions and use the commonized mtk_clk_simple_{probe, remove}(). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230120092053.182923-22-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe()AngeloGioacchino Del Regno1-84/+19
As done with MT8192, migrate MT8186 topckgen away from a custom probe function and use mtk_clk_simple_{probe, remove}(). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230120092053.182923-21-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe()AngeloGioacchino Del Regno1-68/+17
Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-20-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe()AngeloGioacchino Del Regno2-0/+11
In preparation for commonizing topckgen probe on various MediaTek SoCs clock drivers, add the ability to register the MFG MUX notifier in mtk_clk_simple_probe() by passing a custom notifier register function pointer, as this function will be slightly different across different SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-19-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divsAngeloGioacchino Del Regno1-22/+15
Join the two to register them in one shot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230120092053.182923-18-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: mt8186: Join top_adj_div and top_muxesAngeloGioacchino Del Regno1-14/+2
Like done for MT8192, join the two to register them in one shot, as there's no point in doing that separately from one another. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230120092053.182923-17-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: mt8192: Join top_adj_divs and top_muxesAngeloGioacchino Del Regno1-13/+3
These two are both mtk_composite arrays, one dependent on another, but that's something that the clock framework is supposed to sort out and anyway registering them separately isn't going to ease the framework's job in checking dependencies. Put the contents of top_adj_divs in top_muxes to join them together and register them in one shot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-16-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-31clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divsAngeloGioacchino Del Regno1-32/+7
This driver is registered early in clk_mt8192_top_init_early() and then again in clk_mt8192_top_probe(): the difference between the two is that the early one is probed with CLK_OF_DECLARE_DRIVER and the latter is regularly probed as a platform_driver. Knowing that it is not necessary for this platform to register the TOP_CSW_F26M_D2 clock that early, move it to top_divs and register it with the others during platform_driver probe for topckgen; While at it, since the only reason why the early probe existed was to register that clock, remove that entirely - leaving this driver to use only platform_driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-15-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-30 09:24:00 +0300