summaryrefslogtreecommitdiff
path: root/drivers/cxl/core/pci.c
AgeCommit message (Expand)AuthorFilesLines
2024-03-13lib/firmware_table: Provide buffer length argument to cdat_table_parse()Robert Richter1-1/+7
2024-03-13cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter1-36/+41
2024-03-13cxl/pci: Rename DOE mailbox handle to doe_mbRobert Richter1-10/+10
2024-02-17cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS windowRobert Richter1-3/+3
2024-01-29cxl/pci: Skip to handle RAS errors if CXL.mem device is detachedLi Ming1-12/+31
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+36
2023-12-09cxl/cdat: Free correct buffer on checksum errorIra Weiny1-7/+6
2023-11-03cxl/pci: Change CXL AER support check to use native AERTerry Bowman1-2/+2
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-12/+40
2023-10-28cxl: Add support for reading CXL switch CDAT tableDave Jiang1-5/+17
2023-10-28cxl: Add checksum verification to CDAT from CXLDave Jiang1-7/+23
2023-10-28cxl/pci: Disable root port interrupts in RCH modeTerry Bowman1-0/+32
2023-10-28cxl/pci: Add RCH downstream port error loggingTerry Bowman1-0/+96
2023-10-28cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+36
2023-10-28cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman1-13/+31
2023-10-28cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+15
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-2/+2
2023-06-26Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-23/+4
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-2/+2
2023-05-19cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang1-9/+76
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-4/+23
2023-05-13cxl: Add missing return to cdat read error pathDave Jiang1-0/+1
2023-04-23cxl/port: Fix port to pci device assumptions in read_cdat_data()Dan Williams1-6/+7
2023-04-18cxl/pci: Rightsize CDAT response allocationLukas Wunner1-17/+19
2023-04-18cxl/pci: Simplify CDAT retrieval error pathDave Jiang1-11/+12
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner1-22/+5
2023-04-18cxl/pci: Use synchronous API for DOELukas Wunner1-44/+22
2023-04-04cxl/pci: Handle excessive CDAT lengthLukas Wunner1-0/+3
2023-04-04cxl/pci: Handle truncated CDAT entriesLukas Wunner1-4/+9
2023-04-04cxl/pci: Handle truncated CDAT headerLukas Wunner1-1/+1
2023-03-21cxl/pci: Fix CDAT retrieval on big endianLukas Wunner1-13/+13
2023-02-17Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams1-6/+2
2023-02-17cxl/trace: Standardize device information outputIra Weiny1-6/+2
2023-02-15Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-107/+93
2023-02-15cxl/pci: Remove locked check for dvsec_range_allowed()Dave Jiang1-2/+0
2023-02-15cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-3/+6
2023-02-15cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+1
2023-02-15cxl/pci: Refactor cxl_hdm_decode_init()Dave Jiang1-81/+54
2023-02-15cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-11/+7
2023-02-15cxl/pci: Break out range register decoding from cxl_hdm_decode_init()Dave Jiang1-24/+40
2023-02-11Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-5/+0
2023-02-11kernel/range: Uplevel the cxl subsystem's range_contains() helperDan Williams1-5/+0
2023-02-07Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-0/+115
2023-01-05cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-0/+112
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-2/+1
2022-12-04cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-2/+1
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-2/+0
2022-07-20cxl/port: Read CDAT tableIra Weiny1-0/+173
2022-07-10cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-7/+1
2022-05-20cxl/port: Enable HDM Capability after validating DVSEC RangesDan Williams1-15/+152
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-11 01:17:14 +0300