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path: root/drivers/cxl/core/port.c
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2023-02-25Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds1-40/+83
2023-02-11Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams1-39/+53
2023-02-11cxl/dax: Create dax devices for CXL RAM regionsDan Williams1-1/+3
2023-02-11tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams1-0/+2
2023-02-11cxl/region: Add region autodiscoveryDan Williams1-0/+2
2023-02-11cxl/region: Add volatile region creation supportDan Williams1-1/+13
2023-02-11cxl/region: Add a mode attribute for regionsDan Williams1-11/+1
2023-02-11cxl/memdev: Fix endpoint port removalDan Williams1-26/+32
2023-01-27driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman1-4/+4
2023-01-27cxl: fix spelling mistakesRandy Dunlap1-1/+1
2023-01-26cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfsDan Williams1-0/+29
2022-12-05Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams1-3/+6
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-1/+1
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams1-0/+7
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams1-39/+0
2022-12-04cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield1-3/+6
2022-12-04cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-1/+1
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-6/+47
2022-12-03cxl/acpi: Move rescan to the workqueueDan Williams1-2/+17
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter1-14/+34
2022-11-14cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter1-12/+39
2022-11-05cxl/region: Fix 'distance' calculation with passthrough portsDan Williams1-2/+9
2022-08-02cxl/region: Delete 'region' attribute from root decodersDan Williams1-1/+2
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams1-0/+2
2022-07-26cxl/region: Add region driver boiler plateDan Williams1-0/+9
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-0/+1
2022-07-25cxl/region: Program target listsDan Williams1-3/+1
2022-07-25cxl/region: Attach endpoint decodersDan Williams1-7/+3
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams1-0/+16
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams1-0/+9
2022-07-22cxl/region: Add region creation supportBen Widawsky1-0/+39
2022-07-22cxl/mem: Enumerate port targets before adding endpointsDan Williams1-0/+41
2022-07-22cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky1-0/+23
2022-07-22cxl/port: Move dport tracking to an xarrayDan Williams1-49/+36
2022-07-22cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams1-31/+29
2022-07-22cxl/port: Record parent dport when adding portsDan Williams1-12/+15
2022-07-22cxl/port: Record dport in endpoint referencesDan Williams1-17/+35
2022-07-22cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams1-1/+72
2022-07-22cxl/hdm: Track next decoder to allocateDan Williams1-0/+1
2022-07-22cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams1-0/+20
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-10/+21
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams1-7/+27
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-63/+129
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams1-1/+17
2022-07-10cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams1-0/+1
2022-07-10cxl/debug: Move debugfs init to cxl_core_init()Dan Williams1-2/+11
2022-07-10cxl/core: Drop is_cxl_decoder()Dan Williams1-6/+0
2022-07-10cxl/core: Drop ->platform_res attribute for root decodersDan Williams1-22/+6
2022-07-10cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-2/+2
2022-07-09cxl/port: Keep port->uport valid for the entire life of a portDan Williams1-2/+2
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