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path: root/drivers/gpu/drm/i915/display/intel_color.c
AgeCommit message (Expand)AuthorFilesLines
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä1-1/+1
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä1-3/+8
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä1-1/+1
2024-05-27drm/i915: Bury c8_planes_changed() in intel_color_check()Ville Syrjälä1-1/+10
2024-05-27drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()Ville Syrjälä1-0/+5
2024-05-27drm/i915: Plumb the entire atomic state into intel_color_check()Ville Syrjälä1-46/+65
2024-05-24drm/i915: pass dev_priv explicitly to PIPEGCMAXJani Nikula1-6/+6
2024-05-24drm/i915: pass dev_priv explicitly to DSPCNTRJani Nikula1-1/+1
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä1-1/+1
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C22Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C12Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C11_C10Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C02Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C01_C00Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PALETTEJani Nikula1-10/+19
2024-02-09drm/i915/color: Use per-device debugsVille Syrjälä1-5/+6
2023-11-23drm/i915: Fix glk+ degamma LUT conversionsVille Syrjälä1-26/+28
2023-11-23drm/i915: s/clamp()/min()/ in i965_lut_11p6_max_pack()Ville Syrjälä1-1/+1
2023-11-23drm/i915: Adjust LUT rounding rulesVille Syrjälä1-8/+6
2023-10-13drm/i915/dsb: Re-instate DSB for LUT updatesVille Syrjälä1-3/+0
2023-10-10drm/i915: Fix VLV color state readoutVille Syrjälä1-0/+1
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä1-1/+1
2023-09-27drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä1-0/+11
2023-09-27drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä1-6/+24
2023-09-27drm/i915/dsb: Don't use DSB to load the LUTs during full modesetVille Syrjälä1-0/+4
2023-09-07drm/i915: Constify LUT entries in checkerVille Syrjälä1-5/+5
2023-08-25drm/i915/color: move pre-SKL gamma and CSC enable read to intel_colorJani Nikula1-0/+25
2023-08-25drm/i915/color: move SKL+ gamma and CSC enable read to intel_colorJani Nikula1-4/+22
2023-08-25drm/i915: move ILK+ CSC mode read to intel_colorJani Nikula1-0/+17
2023-08-25drm/i915: move HSW+ gamma mode read to intel_colorJani Nikula1-0/+20
2023-08-25drm/i915/color: move CHV CGM pipe mode read to intel_colorJani Nikula1-0/+16
2023-08-25drm/i915/regs: split out intel_color_regs.hJani Nikula1-0/+1
2023-07-27drm/i915/color: Downscale degamma lut values read from hardwareChaitanya Kumar Borah1-0/+8
2023-07-27drm/i915/color: Upscale degamma values for MTLChaitanya Kumar Borah1-1/+18
2023-05-26drm/i915: Implement CTM property support for VLVVille Syrjälä1-2/+168
2023-05-26drm/i915: Always enable CGM CSC on CHVVille Syrjälä1-2/+19
2023-05-26drm/i915: Fix CHV CGM CSC coefficient sign handlingVille Syrjälä1-17/+29
2023-05-26drm/i915: Expose crtc CTM property on ilk/snbVille Syrjälä1-1/+1
2023-05-24drm/i915: Convert INTEL_INFO()->display to a pointerMatt Roper1-15/+16
2023-04-11drm/i915: Implement chv cgm csc readoutVille Syrjälä1-0/+36
2023-04-11drm/i915: Add hardware csc readout for ilk+Ville Syrjälä1-0/+132
2023-04-11drm/i915: Sprinke a few sanity check WARNS during csc assignmentVille Syrjälä1-7/+32
2023-04-11drm/i915: Utilize crtc_state->csc on chvVille Syrjälä1-14/+20
2023-04-11drm/i915: Store ilk+ csc matrices in the crtc stateVille Syrjälä1-24/+62
2023-04-11drm/i915: Start using struct intel_csc_matrix for chv cgm cscVille Syrjälä1-12/+12
2023-04-11drm/i915: Split chv_load_cgm_csc() into piecesVille Syrjälä1-6/+13
2023-04-11drm/i915: Introduce intel_csc_matrix structVille Syrjälä1-97/+91
2023-04-11drm/i915: Fix limited range csc matrixVille Syrjälä1-3/+2
2023-03-21drm/i915: Workaround ICL CSC_MODE sticky armingVille Syrjälä1-1/+43
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-24 02:45:26 +0300