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linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
gpu
/
drm
/
i915
/
display
/
intel_dpll_mgr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2022-04-25
drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
Ville Syrjälä
1
-15
/
+0
2022-04-25
drm/i915: Pass dev_priv to intel_shared_dpll_init()
Ville Syrjälä
1
-5
/
+4
2022-04-25
drm/i915: Make .get_dplls() return int
Ville Syrjälä
1
-123
/
+121
2022-03-10
drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
Ville Syrjälä
1
-10
/
+13
2022-03-10
drm/i915: Replace bxt_clk_div with struct dpll
Ville Syrjälä
1
-34
/
+16
2022-03-10
drm/i915: Store the m2 divider as a whole in bxt_clk_div
Ville Syrjälä
1
-14
/
+13
2022-03-10
drm/i915: Clean up bxt/glk PLL registers
Ville Syrjälä
1
-16
/
+16
2022-03-04
drm/i915: Use designated initializers for bxt_dp_clk_val[]
Ville Syrjälä
1
-7
/
+7
2022-03-04
drm/i915: Remove bxt m2_frac_en
Ville Syrjälä
1
-10
/
+8
2022-03-04
drm/i915: Clean up some struct/array initializers
Ville Syrjälä
1
-9
/
+9
2022-03-04
drm/i915: Move a bunch of stuff into rodata from the stack
Ville Syrjälä
1
-12
/
+12
2022-03-04
drm/i915: Nuke skl_wrpll_context_init()
Ville Syrjälä
1
-10
/
+3
2022-03-02
drm/i915: Use str_on_off()
Lucas De Marchi
1
-2
/
+5
2022-02-18
drm/i915/display/tgl+: Implement new PLL programming step
José Roberto de Souza
1
-13
/
+31
2022-01-19
drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.c
Jani Nikula
1
-0
/
+35
2022-01-12
drm/i915: Move TC PHY registers to their own header
Matt Roper
1
-0
/
+1
2021-10-20
drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFF
José Roberto de Souza
1
-3
/
+3
2021-10-19
drm/i915: Move PCH refclock stuff into its own file
Ville Syrjälä
1
-0
/
+1
2021-09-29
drm/i915/tc: Add/use helpers to retrieve TypeC port properties
Imre Deak
1
-2
/
+3
2021-08-25
drm/i915: Nuke intel_prepare_shared_dpll()
Ville Syrjälä
1
-28
/
+0
2021-08-25
drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()
Ville Syrjälä
1
-10
/
+3
2021-08-12
Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/...
Dave Airlie
1
-494
/
+131
2021-08-03
drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
Imre Deak
1
-1
/
+33
2021-07-30
drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
Lucas De Marchi
1
-492
/
+94
2021-07-22
drm/i915/dg2: Skip shared DPLL handling
Matt Roper
1
-1
/
+4
2021-07-15
Merge branch 'topic/revid_steppings' into drm-intel-gt-next
Matt Roper
1
-1
/
+1
2021-07-15
drm/i915/jsl_ehl: Use revid->stepping tables
Matt Roper
1
-1
/
+1
2021-06-15
drm/i915/adl_p: Add initial ADL_P Workarounds
Clint Taylor
1
-2
/
+2
2021-05-20
drm/i915/adl_p: Add PLL Support
Anusha Srivatsa
1
-17
/
+52
2021-05-05
drm/i915: Don't include intel_de.h from intel_display_types.h
Ville Syrjälä
1
-0
/
+1
2021-04-28
drm/i915/display: move crtc and dpll declarations where they belong
Jani Nikula
1
-0
/
+1
2021-04-14
drm/i915/display: rename display version macros
Lucas De Marchi
1
-1
/
+1
2021-04-14
drm/i915/display: Eliminate IS_GEN9_{BC,LP}
Matt Roper
1
-3
/
+3
2021-03-24
drm/i915/display: Eliminate most usage of INTEL_GEN()
Matt Roper
1
-10
/
+10
2021-03-19
drm/i915/display: Fix a typo
Bhaskar Chowdhury
1
-1
/
+1
2021-03-08
drm/i915: Use pipes instead crtc indices in PLL state tracking
Ville Syrjälä
1
-23
/
+25
2021-03-08
drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
Ville Syrjälä
1
-3
/
+6
2021-01-26
drm/i915/adl_s: Configure DPLL for ADL-S
Aditya Swarup
1
-4
/
+34
2020-12-03
Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org...
Dave Airlie
1
-41
/
+70
2020-11-16
drm: fix some kernel-doc markups
Mauro Carvalho Chehab
1
-1
/
+1
2020-11-16
drm/i915: Use actual readout results for .get_freq()
Ville Syrjälä
1
-33
/
+45
2020-11-16
drm/i915: Introduce intel_dpll_get_hw_state()
Ville Syrjälä
1
-3
/
+17
2020-11-05
drm/i915/ehl: Implement W/A 22010492432
Tejas Upadhyay
1
-5
/
+8
2020-10-16
drm/i915/dg1: Enable DPLL for DG1
Lucas De Marchi
1
-4
/
+4
2020-10-16
drm/i915/dg1: Add and setup DPLLs for DG1
Aditya Swarup
1
-4
/
+38
2020-10-14
drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Tejas Upadhyay
1
-8
/
+8
2020-10-06
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
Imre Deak
1
-16
/
+25
2020-10-06
drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
Imre Deak
1
-0
/
+13
2020-09-16
drm/i915/pll: Centralize PLL_ENABLE register lookup
Anusha Srivatsa
1
-17
/
+18
2020-09-08
Merge tag 'v5.9-rc4' into drm-next
Dave Airlie
1
-4
/
+4
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