summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_lvds.c
AgeCommit message (Expand)AuthorFilesLines
2023-06-02drm/i915/lvds: switch to drm_edid_read_switcheroo()Jani Nikula1-11/+2
2023-05-05drm/i915/display: Add new member to configure PCON color conversionAnkit Nautiyal1-0/+1
2023-04-20drm/i915: Namespace pfit registers properlyVille Syrjälä1-1/+1
2023-03-30drm/i915/pps: split out PPS regs to a separate fileJani Nikula1-0/+1
2023-02-18drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä1-1/+1
2023-01-31drm/i915/lvds: s/pipe_config/crtc_state/Ville Syrjälä1-23/+23
2023-01-31drm/i915/lvds: s/intel_encoder/encoder/ etc.Ville Syrjälä1-70/+64
2023-01-31drm/i915/lvds: s/dev_priv/i915/Ville Syrjälä1-57/+54
2023-01-31drm/i915/lvds: Fix whitespaceVille Syrjälä1-14/+14
2023-01-31drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä1-0/+1
2023-01-31drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä1-2/+2
2023-01-31drm/i915/lvds: Use intel_de_rmw()Ville Syrjälä1-8/+4
2023-01-31drm/i915/lvds: Split long linesVille Syrjälä1-3/+7
2023-01-26drm/i915/panel: move panel fixed EDID to struct intel_panelJani Nikula1-6/+5
2023-01-26drm/i915/bios: convert intel_bios_init_panel() to drm_edidJani Nikula1-1/+1
2023-01-26drm/i915/edid: convert DP, HDMI and LVDS to drm_edidJani Nikula1-17/+29
2022-12-09drm/i915: Do panel VBT init early if the VBT declares an explicit panel typeVille Syrjälä1-2/+2
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-10-11drm/i915/display: remove drm_device aliasesAndrzej Hajda1-6/+5
2022-09-28drm/i915: Allow alternate fixed modes always for LVDSVille Syrjälä1-2/+1
2022-09-28drm/i915: Simplify intel_panel_add_edid_alt_fixed_modes()Ville Syrjälä1-2/+1
2022-09-26drm/i915: Clean up connector->*_allowed setupVille Syrjälä1-2/+0
2022-09-26drm/i915: Extract intel_attach_scaling_mode_property()Ville Syrjälä1-9/+1
2022-09-26drm/i915: Extract intel_lvds_add_properties()Ville Syrjälä1-7/+14
2022-09-26drm/i915: Pass intel_encoder to to_lvds_encoder()Ville Syrjälä1-9/+9
2022-08-31drm/i915: move vbt to display.vbtJani Nikula1-2/+2
2022-06-20drm/i915/bios: calculate panel type as per child device index in VBTAnimesh Manna1-1/+1
2022-06-01drm/i915: Accept more fixed modes with VRR panelsVille Syrjälä1-1/+2
2022-05-27drm/i915/bios: Determine panel type via PNPID matchVille Syrjälä1-1/+2
2022-05-27drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä1-2/+4
2022-03-31drm/i915: Allow static DRRS on LVDSVille Syrjälä1-1/+2
2022-03-31drm/i915: Combine the EDID fixed_mode+downclock_mode lookup into oneVille Syrjälä1-1/+1
2022-03-31drm/i915: Put fixed modes directly onto the panel's fixed_modes listVille Syrjälä1-18/+13
2022-03-29drm/i915: Extract intel_panel_encoder_fixed_mode()Ville Syrjälä1-6/+1
2022-03-29drm/i915: Rename intel_panel_vbt_fixed_mode()Ville Syrjälä1-1/+1
2022-03-29drm/i915: Use intel_panel_preferred_fixed_mode() moreVille Syrjälä1-5/+6
2022-03-29drm/i915: Use DRM_MODE_FMT+DRM_MODE_ARG()Ville Syrjälä1-2/+2
2022-03-29drm/i915: Pass intel_connector to intel_panel_{init,fini}()Ville Syrjälä1-1/+1
2022-03-15drm/i915: Introduce intel_panel_get_modes()Ville Syrjälä1-8/+1
2022-03-15drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä1-1/+2
2022-03-15drm/i915/lvds: Pass fixed_mode to compute_is_dual_link_lvds()Ville Syrjälä1-3/+4
2021-10-01drm/i915/dpll: move dpll modeset asserts to intel_dpll.cJani Nikula1-0/+1
2021-10-01drm/i915/fdi: move fdi modeset asserts to intel_fdi.cJani Nikula1-0/+1
2021-09-30drm/i915: Introduce intel_panel_compute_config()Ville Syrjälä1-2/+3
2021-09-30drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVOVille Syrjälä1-4/+6
2021-08-26drm/i915/panel: mass rename functions to have intel_panel_ prefixJani Nikula1-5/+2
2021-08-26drm/i915/backlight: mass rename functions to have intel_backlight_ prefixJani Nikula1-5/+5
2021-08-26drm/i915/backlight: extract backlight code to a separate fileJani Nikula1-0/+1
2021-06-24drm/i915: s/intel_crtc/crtc/Ville Syrjälä1-2/+2
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1