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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2023-04-14drm/i915/color: Fix typo for Plane CSC indexesChaitanya Kumar Borah1-2/+2
2023-04-06Merge tag 'drm-intel-next-2023-04-06' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter1-1221/+22
2023-04-06Merge tag 'drm-intel-gt-next-2023-04-06' of git://anongit.freedesktop.org/drm...Daniel Vetter1-2/+12
2023-04-04drm/i915/psr: split out PSR regs to a separate fileJani Nikula1-249/+0
2023-04-04drm/i915/wm: split out SKL+ watermark regs to a separate fileJani Nikula1-149/+0
2023-03-31drm/i915: Define cursor chicken regVille Syrjälä1-0/+2
2023-03-31drm/i915: Document that PLANE_CHICKEN are for tgl+Ville Syrjälä1-2/+2
2023-03-30drm/i915/dsb: split out DSB regs to a separate fileJani Nikula1-56/+0
2023-03-30drm/i915/fdi: split out FDI regs to a separate fileJani Nikula1-141/+0
2023-03-30drm/i915/aux: split out DP AUX regs to a separate fileJani Nikula1-73/+0
2023-03-30drm/i915/tv: split out TV regs to a separate fileJani Nikula1-479/+0
2023-03-30drm/i915/pps: split out PPS regs to a separate fileJani Nikula1-67/+0
2023-03-28drm/i915/gsc: implement wa 14015076503Daniele Ceraolo Spurio1-2/+12
2023-03-28Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-13/+0
2023-03-28drm/i915/ips: Add i915_ips_false_color debugfs fileVille Syrjälä1-1/+2
2023-03-27drm/i915/reg: use the correct register to access SAGV block timeVinod Govindapillai1-1/+1
2023-03-27drm/i915/reg: fix QGV points register access offsetsVinod Govindapillai1-2/+3
2023-03-25drm/i915: Move PLANE_BUG_CFG bit definitions to the correct placeVille Syrjälä1-5/+5
2023-03-25drm/i915/dpt: Add a modparam to disable DPT via the chicken bitVille Syrjälä1-0/+2
2023-03-24Merge tag 'drm-intel-next-2023-03-23' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter1-24/+63
2023-03-24drm/i915: Add PLANE_CHICKEN registersVille Syrjälä1-0/+9
2023-03-22Merge tag 'drm-intel-gt-next-2023-03-16' of git://anongit.freedesktop.org/drm...Dave Airlie1-9/+0
2023-03-17drm/i915: Clean up skl+ plane alpha bitsVille Syrjälä1-2/+3
2023-03-17drm/i915: Define vlv/chv sprite plane SURFLIVE registersVille Syrjälä1-0/+3
2023-03-17drm/i915: Define skl+ universal plane SURFLIVE registersVille Syrjälä1-0/+9
2023-03-17drm/i915: Program VLV/CHV PIPE_MSA_MISC registerVille Syrjälä1-0/+6
2023-03-17drm/i915: Define more pipe timestamp registersVille Syrjälä1-1/+17
2023-03-17drm/i915: s/PIPEMISC/PIPE_MISC/Ville Syrjälä1-17/+17
2023-03-17drm/i915: Stop using pipe_offsets[] for PIPE_MISC*Ville Syrjälä1-2/+2
2023-03-15Merge tag 'drm-intel-next-2023-03-07' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-670/+231
2023-03-13drm/i915/mtl: Disable MC6 for MTL A stepBadal Nilawar1-9/+0
2023-03-09drm/i915/display/mtl: Program latch to phy resetJosé Roberto de Souza1-0/+2
2023-03-09drm/i915/mtl: Fix Wa_16015201720 implementationRadhakrishna Sripada1-3/+5
2023-03-07drm/i915: Get rid of the gm45 HPD live state nonsenseVille Syrjälä1-12/+1
2023-03-06drm/i915/display: split out DSC and DSS registersJani Nikula1-450/+0
2023-02-20drm/i915/dsb: Define more DSB registersVille Syrjälä1-2/+48
2023-02-18drm/i915: Define transcoder timing register bitmasksVille Syrjälä1-0/+24
2023-02-18drm/i915: Define the "unmodified vblank" interrupt bitVille Syrjälä1-0/+1
2023-02-18drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä1-53/+53
2023-02-18drm/i915: Give CPU transcoder timing registers TRANS_ prefixVille Syrjälä1-46/+46
2023-02-15drm/i915/dgfx, mtl+: Disable display functionality if the display is not presentImre Deak1-0/+3
2023-02-02Merge tag 'drm-intel-gt-next-2023-02-01' of git://anongit.freedesktop.org/drm...Dave Airlie1-4/+0
2023-01-31drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä1-54/+0
2023-01-31drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä1-24/+22
2023-01-27drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()Lucas De Marchi1-4/+5
2023-01-27drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()Lucas De Marchi1-3/+5
2023-01-27drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()Lucas De Marchi1-7/+9
2023-01-27drm/i915: Convert pll macros to _PICK_EVEN_2RANGESLucas De Marchi1-30/+29
2023-01-27drm/i915: Fix coding style on DPLL*_ENABLE definesLucas De Marchi1-10/+10
2023-01-25Merge drm/drm-next into drm-intel-nextJani Nikula1-0/+3
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